Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)

Many telecommunication applications require a fast switching, fine tuning and superior quality sinusoidal signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and electronic communication knowledge, and apply them in a practical environment. It does so by providing a tutorial on designing and implementing a DDS on an FPGA using Xilinx’s ISE software. The thesis also examines the final results and shows the unwanted spurs that are generated. Since this is purely a digital design, it does not implement a digital-to-analog converter (DAC) or a low-pass filter. Using a Virtex 6 design for the FPGA, one can achieve close to perfect sinusoids, without any phase change, with varying frequency tuning words (FTWs).

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2013

Author dc:creator

• Bhagat, Karan

Contributors dc:contributor

• Schutt-Ainé, José E.

• simulation
• direct digital synthesis (DDS)
• direct digital synthesizer
• direct digital synthesizer (DDS)
• Field-Programmable Gate Array (FPGA)
• circuit design
• digital circuit design
• design flow
• design
• Implementation
• Verilog
• tutorial
• phase accumulator
• sine lookup table
• phase truncation
• spurs
• place and route
• ModelSim
• Xilinx
• Virtex

Statement dc:rights

• Copyright 2012 Karan Bhagat

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/42300

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/42300