Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 75 for “"Verilog"”.
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Modeling photonic links in Verilog-A
… of photonic device models is developed in Verilog-A for use in seamless simulation of opto-electronic circuits in Cadence.
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Sieve : an XML-based structural Verilog rules check tool
… units that check that the design is structural Verilog, and units that check leaf signal rules. A flexible input format for describing the rules is also developed so the tool can be easily adapted for new conventions and new chip designs. The input to the tools is a Verilog design file. Icarus …
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Compact modeling of circuits and devices in Verilog-A
… Two contributions related to compact modeling in Verilog-A are presented in this thesis. The first contribution is an analysis of the feasibility and performance of the Verilog-A language in the context of implementing reduced order models. Reduced order models are a class of purely mathematical …
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Implementation of the Intel 486 SX microprocessor in Verilog hardware description language
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.
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Static analysis for circuit families
… hardware description languages (HDLs) like Verilog and VHDL must be significantly enhanced. This thesis pinpoints some of the main shortcomings of the latest Verilog standard (IEEE 1364-2005) and shows how to overcome them by extending the language in a backward compatible way. To be able to …
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An Exploration of the Feasibility of FPGA Implementation of Face Recognition Using Eigenfaces
… for FPGA implementation. We then develop the Verilog module for each of these modules and test their functionality using a Verilog Simulator and finally we discuss the feasibility of FPGA implementation. Implementing the face recognition technology in an FPGA would mean that they would require …
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An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
… All implementation was done in Bluespec System Verilog hardware synthesis language for placement on FPGA. Furthermore, this document analyzes the main tradeoffs and major challenges involved in building and integrating such a system.
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FPGA-based digital controller for dc-dc converter
… The control algorithm has been developed using Verilog language based on the voltage control loop. The FPGA switching controller has been designed as simple as possible while maintaining the accuracy and dynamic response. The DE1 board is used to control the main circuit. Simulations and …
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Implementace 10 GbE technologie použitím zařízení s FPGA modulem
… prostředí použitím HDL jazyků (VHDL a Verilog) a IP jádra firmy Altera.
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Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics …
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PHDL : a Python Hardware Design framework
… with less complexity than a corresponding Verilog implementation, while achieving better portability and platform specific optimizations.
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Design study of a novel computer instruction execution unit
… into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.
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A MIPS datapath simulator for enhancing visual learning of computer architecture
… simulation of the MIPS datapath through Verilog.
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Python based FPGA design-flow
… MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to …
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Design and prototype of an all digital system for baseband FM multiplex signal demodulation
… numerical computation software; implemented in Verilog Hardware Description Language; and tested using the digital to analog converters (DACs) on the Xilinx Spartan-3AN Starter Kit. The oscilloscope images at the end of this report show that the implemented system can successfully demodulate the …
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A PCI Express to PCIX Bridge optimized for performance and area
… architectural design, development of Verilog and Vera models, thorough module-level verification, the development of a PCI Express/PCIX system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM …
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The design of sensor interface circuits for electrochemical impedance spectroscopy
… an Ultra-Microband (UMB) sensor, implemented in Verilog-A, and proposes a fast, high-accuracy methodology for conducting EIS based on the Fast Fourier Transform (FFT). This approach aims to fulfill the requirements of portable, real-time, label-free EIS biomedical detection. The work begins by …
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Design & Analysis of Mixed-mode Integrated Circuit for Pulse-shape Discrimination
… We model this mixed-mode PSD system using Verilog-A and simulate its performance using Cadence Spectre with real detector waveform data as the input. We show that our mixed-mode PSD system is capable of discriminating between neutrons and gamma rays at least as well as state of the art DSP …
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Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single- Threaded C Programs
… like C and hardware description languages like Verilog. We propose to bridge this gap with Twill, a truly automatic hybrid compiler that can take advantage of the parallelism inherent in these platforms. Twill can extract long-running threads from single threaded C code and distribute these …
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Návrh a implementace opatření proti útokům postranními kanály na platformě FPGA
… jazyků HDL (Hardware Description Language) jako Verilog nebo VHDL. Poté je zde představen obecný přehled o postranních kanálech a jejich typech, opatřeních proti útokům a podrobný popis bezpečnostních technik. Další kapitolou je kryptografické schéma AES a popsání jeho operací. Je zde věnována …
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