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Showing 1 to 9 of 9 for “"ModelSim"”.

  1. Implementation of Orthogonal Frequency Division Multiplexing with FPGA

    … language (VHDL) under development environment of ModelSim, and then implemented onto Altera cyclone II EP2C35F672C6. The FFT accuracy is measured by comparing outputs from ModelSim to Matlab. The performance of the developed OFDM is evaluated in a wireless communication testbed.</p>

    arkansas Repository record for Implementation of Orthogonal Frequency Division Multiplexing with FPGA (opens in a new tab)

  2. Implementace 10 GbE technologie použitím zařízení s FPGA modulem

    … použitím VHDL jazyka, spouštěnou v Mentor ModelSIM. Text práce je rozdělený na dvě části: • První část se věnuje shrnutí potřebné teorie pro implementaci protokolu - ISO/OSI model a protokol IEEE 802.3 Ethernet vycházející z tohoto modelu, konkrétně standard 10GBASE-R. Také popisuje …

    brno-tech Repository record for Implementace 10 GbE technologie použitím zařízení s FPGA modulem (opens in a new tab)

  3. SERIAL PROTOCOL BRIDGE

    … have been coded in VHDL and simulated using ModelSim Altera 6.5e. Further these modules were compiled for EP4CE115F29C7 FPGA chip on Cyclone IV Altera DE115 board using Quartus II.</p>

    ohiolink Repository record for SERIAL PROTOCOL BRIDGE (opens in a new tab)

  4. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)

    … using Altera Quartus II FPGA design software and ModelSim Simulator. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with novel truncation spurs-free structure. By comparing the …

    uiuc Repository record for Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA) (opens in a new tab)

  5. Easy-filter: A Design, Verification, and Validation Tool for Finite Impulse Response (FIR) Filter

    … code of the FIR filter and simulate using Modelsim. The second step is to validate this design by comparing its results against already existing well established MATLAB's results. Filters of some sorts are essential to the operation of most electronic circuits. Our proposed system can save …

    texas-state Repository record for Easy-filter: A Design, Verification, and Validation Tool for Finite Impulse Response (FIR) Filter (opens in a new tab)

  6. Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security

    … Functional verification has been done using Modelsim and Field-Programmable Gate Array (FPGA). 2) Implemented two different power analysis attacks on both NCL S-Box and conventional synchronous S-Box. 3) Developed a novel approach based on stochastic logics to enhance the resistance against …

    must-thes Repository record for Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security (opens in a new tab)

  7. Soft Computing To Sensor Network Reliability, Systems And Their Fpga Implementation

    … models was done using Xilinx's Spartan-3 FPGA, ModelSim-XE and SynaptiCAD-VeriLoggerPRO. It is hoped that proposed techniques will go a long way in finding applications in SN areas.</p>

    wayne-thes Repository record for Soft Computing To Sensor Network Reliability, Systems And Their Fpga Implementation (opens in a new tab)

  8. Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)

    Many telecommunication applications require a fast switching, fine tuning and superior quality sinusoidal signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and …

    uiuc Repository record for Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA) (opens in a new tab)