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Showing 1 to 20 of 47 for “"Virtex"”.
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A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs
… set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the …
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High-speed dynamic partial reconfiguration for field programmable gate arrays
… (i) one targeting the Hard IP PowerPC405 on Virtex-4, (ii) a second targeting the Soft IP MicroBlaze on Virtex-5, (iii) a third targeting the Hard IP PowerPC440 on Virtex-5, and (iv) a fourth system targets the Hard IP PowerPC440 on Virtex-5 capable of adaptive feedback. The adaptive feedback …
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Implementation of Directional Median Filtering using Field Programmable Gate Arrays
… implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, …
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JHDLBits: An Open-Source Model for FPGA Design Automation
… on how the core components -- JHDL, JBits3 for Virtex-II, the ADB connectivity database, and VTsim, a Virtex-II device simulator -- are linked together to provide an integrated design environment. Strategies and philosophies of the open source movement are also examined to successfully establish …
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Open-Source Bitstream Generation for FPGAs
… primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work.
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An 8 GHz Ultra Wideband Transceiver Testbed
… the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non real-time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The overall objective is to demonstrate a testbed that will …
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Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)
… decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the …
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Accelerating software radio astronomy FX correlation with GPU and FPGA co-processors
… with one using reconfigurable hardware (Xilinx Virtex 4LXlOO) and the other uses a graphics processor (Nvidia 9800GT). The objective of a radio astronomy correlator is to compute the complex valued correlation products for each baseline which can be used to reconstruct the sky's radio brightness …
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A timeshared, runtime reconfigurable hardware co-processing architecture
… reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.
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Mixed-precision architecture for flexible neural network accelerators
… the performance of the system is evaluated on a Virtex-9 UltraScale FPGA by running state-of-the-art neural networks.
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Fault tolerant design implementation on radiation hardened by design SRAM-Based FPGAs
… design and testing flexibility. The Xilinx Virtex-5QV is the first commercially available Radiation Hardened By Design (RHBD) SRAM-based FPGA; however, not all of its internal components are hardened against radiation-induced errors. This thesis examines and quantifies the additional …
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Runtime Intellectual Property Protection on Programmable Platforms
… in a secure video messaging device on top of a Virtex-II Pro development system.
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All Digital FM Demodulator
… block to avoid the need for a DAC. The Xilinx virtex-7 FPGA has been used as the reference device for the work. The circuit is validated through behavioral simulations and the results conclude the proposed circuit demodulates the targeted FM channel and provides the spectrum information for the …
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Circuit implementations for high-efficiency video coding tools
… synthesis results in 40nm CMOS technology and Virtex-6 FPGA platform are presented.
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Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)
… converter (DAC) or a low-pass filter. Using a Virtex 6 design for the FPGA, one can achieve close to perfect sinusoids, without any phase change, with varying frequency tuning words (FTWs).
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A Device-Level FPGA Simulator
… in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain …
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Improving Field-Programmable Gate Array Scaling Through Wire Emulation
… is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis.
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An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core
… that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process …
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Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-programmable Gate Arrays
… the fine-grain reconfigurable resources of Virtex FPGAs, they are easily portable to other FPGAs with similar reconfigurable fabrics without any major modifications. The pipelined designs of these two operations are evaluated in terms of area, throughput, and dynamic power consumption as a …
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Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer
… channelizer is implemented on the external Virtex 5 FPGA, while the IEEE 802.15.4 receiver is implemented in GNU Radio on the host. The first case demonstrates how spare resources in USRP's FPGA can be used to implement signal processing task while still interfacing with GNU Radio. The …
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