ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology

This thesis describes a study designed to enhance the understanding of the reliability of doubly-stacked NMOS transistors under Charged Device Model (CDM) electrostatic discharge (ESD) conditions. Stacked NMOS are commonly used in high-voltage tolerant output drivers. The transistors used for this study are fabricated in a FinFET CMOS process. The test structures were designed such that the robustness of doubly-stacked NMOS devices could be evaluated as a function of the applied gate bias and the layout style. Very-Fast Transmission Line Pulse (VF TLP) measurements were used to evaluate the ESD robustness and the dynamic response. Based on the experimental results and subsequent analysis, design recommendations and a biasing strategy for cascoded output drivers are proposed. The objective is to improve the ESD reliability of high-voltage tolerant output drivers.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Guo, Yuanqi

Contributors dc:contributor

• Rosenbaum, Elyse

• ESD
• Stacked NMOS
• high-voltage tolerant output drivers
• CDM
• VF-TLP

Statement dc:rights

• Copyright 2025 Yuanqi Guo

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/129479

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F129479