{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129479"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129479","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01","abstract_has_math":false,"creators":["Guo, Yuanqi"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-01-13","date_published":"2025-01-13","updated_at":"2026-07-22T22:25:05Z","subjects":["ESD","Stacked NMOS","high-voltage tolerant output drivers","CDM","VF-TLP"],"languages":["en","eng"],"rights":["Copyright 2025 Yuanqi Guo"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129479","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Guo, Yuanqi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-01-13","2025-05"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["ESD","Stacked NMOS","high-voltage tolerant output drivers","CDM","VF-TLP"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Yuanqi Guo"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129479"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01","The student, Yuanqi Guo, accepted the attached license on 2025-01-06 at 15:47.","The student, Yuanqi Guo, submitted this Thesis for approval on 2025-01-06 at 16:01.","This Thesis was approved for publication on 2025-01-13 at 13:46.","DSpace SAF Submission Ingestion Package generated from Vireo submission #21251 on 2025-10-19 at 19:13:45","This thesis describes a study designed to enhance the understanding of the reliability of doubly-stacked NMOS transistors under Charged Device Model (CDM) electrostatic discharge (ESD) conditions. Stacked NMOS are commonly used in high-voltage tolerant output drivers. The transistors used for this study are fabricated in a FinFET CMOS process. The test structures were designed such that the robustness of doubly-stacked NMOS devices could be evaluated as a function of the applied gate bias and the layout style. Very-Fast Transmission Line Pulse (VF TLP) measurements were used to evaluate the ESD robustness and the dynamic response. Based on the experimental results and subsequent analysis, design recommendations and a biasing strategy for cascoded output drivers are proposed. The objective is to improve the ESD reliability of high-voltage tolerant output drivers."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Guo, Yuanqi"],"dc:date":["2025-01-13","2025-05"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01","The student, Yuanqi Guo, accepted the attached license on 2025-01-06 at 15:47.","The student, Yuanqi Guo, submitted this Thesis for approval on 2025-01-06 at 16:01.","This Thesis was approved for publication on 2025-01-13 at 13:46.","DSpace SAF Submission Ingestion Package generated from Vireo submission #21251 on 2025-10-19 at 19:13:45","This thesis describes a study designed to enhance the understanding of the reliability of doubly-stacked NMOS transistors under Charged Device Model (CDM) electrostatic discharge (ESD) conditions. Stacked NMOS are commonly used in high-voltage tolerant output drivers. The transistors used for this study are fabricated in a FinFET CMOS process. The test structures were designed such that the robustness of doubly-stacked NMOS devices could be evaluated as a function of the applied gate bias and the layout style. Very-Fast Transmission Line Pulse (VF TLP) measurements were used to evaluate the ESD robustness and the dynamic response. Based on the experimental results and subsequent analysis, design recommendations and a biasing strategy for cascoded output drivers are proposed. The objective is to improve the ESD reliability of high-voltage tolerant output drivers."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129479"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Yuanqi Guo"],"dc:subject":["ESD","Stacked NMOS","high-voltage tolerant output drivers","CDM","VF-TLP"],"dc:title":["ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:05Z"}