Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 109 for “"ESD"”.
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ESD circuit design and measurement techniques
… used to measure reverse recovery in a 65 nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of …
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Detection of ESD-induced soft errors
IEC-61000-4-2 compliant ESD discharges are performed on a microcontroller. The effect of ESD-induced noise on a digital system having a workload is examined. UART interface present on-chip is used for memory and register readout. Hardware voltage monitors developed previously are included in the …
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Investigation of system-level ESD-induced failures
Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets …
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ESD Protected SiGe HBT RFIC Power Amplifiers
… integrated circuits to electrostatic discharge (ESD) induced damages has justified the use of dedicated on-chip protection circuits. Design of robust protection circuits remains a challenging task because ESD failure mechanisms have become more acute as device dimensions continue to shrink. A …
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Compact model of ESD diode for circuit simulation
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-12-01
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High-voltage ESD PNP clamp simulation and design
… this work high-voltage Electrostatic discharge (ESD) PNPs are studied through TCAD simulation and device measurement. PNPs for three different voltage classes, 16 V, 65 V, and 100 V, in a 0.5-µm Bipolar CMOS DMOS (BCD) technology are used as the context for the study. The PNPs are varied in …
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Investigating soft failures induced by system-level ESD
Hardware and application-level manifestations of ESD soft failures were characterized for three single-board computers. ESD events were generated following the system-level ESD standard (IEC 61000-4-2), matching real-world testing and events. Soft failures resulting from ESD were seen on all …
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Investigation of system-level ESD induced soft failures
Electrostatic discharge (ESD) is a common phenomenon that can have negative implications for the performance of systems during operation. ESD is a brief, high-current stress that when applied to a functional system, can cause a variety of problems ranging from temporary system malfunction to …
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System level ESD failure mechanisms, analysis and test method
… discharge current and the transient fields of an ESD generator in the contact mode are numerically simulated using the FDTD method...The second and the third papers derived a reference ESD event for human-metal ESD from measured discharges...In the fourth paper, a three dimensional ESD scanning …
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Modeling and Analysis Methods for ESD and EMI Problems
<p>"Electrostatic discharge (ESD) failures and Electromagnetic interference (EMI) problems are becoming more critical in electronic devices and large systems. In this work, four studies are presented to model and analyze ESD and EMI problems.</p> <p>First, a simplified physical-based model for …
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Characterization and modeling of ESD events, risk and protection
<p>“The ESD (Electrostatic discharge) failures have been raising critical reliability problems in electronic devices design. However, not all the ESD scenarios have been specified by the IEC standard and the characterizations of the ESD risk for different scenarios are essential to evaluate the ESD …
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Uncalibrated TCAD methodology for analysis of ESD protection devices
… for simulation of electrostatic discharge (ESD) devices is presented. The methodology addresses TCAD setup issues including device construction, boundary conditions, and choosing a physical model and parameters. A major trade-off between computation complexity and accuracy, 2D vs. 3D …
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Failures caused by supply fluctuations during system-level ESD
… against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be caused by ESD-induced noise on signal inputs and …
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Evaluation of the practicality of system efficient ESD design
… 61000-4-2 discharge. Electrostatic discharge (ESD) gun zaps are applied to the test board; simulated and measured waveforms are compared.
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Understanding, modeling, and mitigating system-level ESD in integrated circuits
… effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important tool for achieving quality designs …
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Measurement, Modeling, and Simulation of Fast Transients in ESD Devices
… including measuring the turn-on time of LVTSCR ESD protection devices. A circuit simulation macromodel for use in circuit simulation tools has also been incorporated into the Illinois Electrothermal Simulator (iETSIM). A complete discussion of SCRs as ESD protection devices and our …
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Logic upset induced by substrate current during power-on ESD
… during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention …
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Victim structures for predicting the ESD reliability of IO circuits
Compact, wafer-level ESD victim circuits that fail similarly to real IO circuits are used to validate the performance of ESD protection schemes in a 65-nm process technology. Electrical failure analysis identifies the device that fails during the ESD testing. Effects of circuit topologies and …
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Design for ESD Reliability in High-Frequency Mixed-Signal Integrated Circuits
The design of on-chip ESD protection has become increasingly critical and difficult because of shrinking device feature sizes, high operating speed, and system-on-a-chip (SoC) environment. A complex ESD protection network can be easily exposed during normal operation and can cause the degradation …
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Automated testing and machine-learning-based modeling of air discharge ESD
… of air discharge electrostatic discharge (ESD). This work corroborates conclusions of previous works and presents new insights into the effects of approach speed on ESD. A methodology for machine-learning-based ESD modeling is presented. Models are validated with a high degree of accuracy …
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