Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

<p>This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.</p>

Name thesis:degree_name

MS

Grantor dc:publisher

Brigham Young University - Provo

Author dc:creator

• Bartholomew, David Ray

• design
• high speed
• mixed-signal
• CMOS
• mutliplier
• circuit
• circuit design
• short-channel
• PMOS
• transistors
• MOSFET
• Cadence Design Systems
• nonlinearity
• filtering
• digital to analog conversion
• linear equalization
• short-channel effects
• Electrical and Computer Engineering

Language dc:language

English

Repository record dc:identifier

https://scholarsarchive.byu.edu/etd/126

OAI identifier oai:identifier

oai:scholarsarchive.byu.edu:etd-1125