This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
","abstract_html":"<p>This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.</p>","abstract_has_math":false,"creators":["Bartholomew, David Ray"],"institution":"Brigham Young University - Provo","degree_name":"MS","degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"","date_published":null,"updated_at":"2026-07-24T01:27:25Z","subjects":["design","high speed","mixed-signal","CMOS","mutliplier","circuit","circuit design","short-channel","PMOS","transistors","MOSFET","Cadence Design Systems","nonlinearity","filtering","digital to analog conversion","linear equalization","short-channel effects","Electrical and Computer Engineering"],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarsarchive.byu.edu/etd/126","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Bartholomew, David Ray"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2004-03-12T08:00:00Z"]},{"key":"dc:publisher","label":"Institution","values":["Brigham Young University - Provo"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["MS"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["design","high speed","mixed-signal","CMOS","mutliplier","circuit","circuit design","short-channel","PMOS","transistors","MOSFET","Cadence Design Systems","nonlinearity","filtering","digital to analog conversion","linear equalization","short-channel effects","Electrical and Computer Engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarsarchive.byu.edu/etd/126","https://scholarsarchive.byu.edu/context/etd/article/1125/viewcontent/ETD_CISOPTR_94.pdf"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering"]},{"key":"dc:description.abstract","label":"Abstract","values":["This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
"]},{"key":"dc:format","label":"Dc Format","values":["application:pdf"]},{"key":"dc:source","label":"Dc Source","values":["Brigham Young University - Provo"]},{"key":"dc:title","label":"Title","values":["Design of a High Speed Mixed Signal CMOS Mutliplying Circuit"]}]}],"canonical_facts":{"dc:creator":["Bartholomew, David Ray"],"dc:date":["2004-03-12T08:00:00Z"],"dc:description":["Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering"],"dc:description.abstract":["This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
"],"dc:format":["application:pdf"],"dc:identifier":["https://scholarsarchive.byu.edu/etd/126","https://scholarsarchive.byu.edu/context/etd/article/1125/viewcontent/ETD_CISOPTR_94.pdf"],"dc:language":["English"],"dc:publisher":["Brigham Young University - Provo"],"dc:source":["Brigham Young University - Provo"],"dc:subject":["design","high speed","mixed-signal","CMOS","mutliplier","circuit","circuit design","short-channel","PMOS","transistors","MOSFET","Cadence Design Systems","nonlinearity","filtering","digital to analog conversion","linear equalization","short-channel effects","Electrical and Computer Engineering"],"dc:title":["Design of a High Speed Mixed Signal CMOS Mutliplying Circuit"],"dc:type":["Thesis"],"thesis:degree_name":["MS"]},"updated_at":"2026-07-24T01:27:25Z"}