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Showing 1 to 20 of 380 for “"MOS"”.
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Logic optimization of MOS networks
… synthesis tools for the logic optimization of MOS networks.
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Functional models for MOS VLSI circuits
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design applications for VLSI circuits is considered. A method for the automatic generation of functional models for switch- and gate-level circuits is presented. In addition, the use of these models is …
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MOS-bipolar composite power switching devices
Two MOS-Bipolar composite power semiconductor switching devices are proposed and experimentally demonstrated. These devices feature high voltage and high current capabilities, fast switching speeds, simple gate drive requirements, savings in chip area, reverse bias second breakdown ruggedness and …
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Technologies for Scaling Silicon-MOS Quantum Processors
… presented in-depth for the scale-up of Silicon-MOS based quantum dot devices for quantum computation. Firstly, a passive filter/combiner is developed that behaves as a DC-coupled bias tee. This allows for linear combination of DC-bias voltages with broadband pulses (DC - 500 MHz) from an …
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Logic Design Methods for Irredundant Mos Networks
Made available in DSpace on 2014-12-13T18:02:06Z (GMT). No. of bitstreams: 1 7913492.pdf: 9772259 bytes, checksum: d1aaeacb841e787cd2fa8b56499068e8 (MD5) Previous issue date: 1978
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1/f surface noise in Mos transistors
Made available in DSpace on 2014-12-08T22:24:04Z (GMT). No. of bitstreams: 1 6706631.pdf: 2926893 bytes, checksum: 8233428a948c077c63135fb22d7a5b0e (MD5) Previous issue date: 1966
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Optimum gate arrangements for MOS standardized layouts
Optimization of size is an important topic of research in the engineering of digital circuits. The field effect transistor (FET) is making an important contribution in this area. In this paper, the basic properties of the FET which pertain to digital circuits will be examined. The problems …
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Fast timing simulation of MOS VLSI circuits
… simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract …
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Large signal linearity of scaled MOS transistors
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1987.
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Switch-Level Timing Simulation of Mos Vlsi Circuits
… (VLSI) circuits of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented …
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Synthesis of Logic Networks With Mos Complex Cells
Made available in DSpace on 2014-12-10T20:13:35Z (GMT). No. of bitstreams: 1 7309985.pdf: 6936837 bytes, checksum: 0fc44cceddbd1dc2ac490315fae5033c (MD5) Previous issue date: 1972
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Macromodeling and optimization of digital MOS VLSI circuits
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1985.
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MoS₂ electronics : technology, high yield circuits and applications
… electronics based on single-layer MoS₂ synthesized by chemical vapor deposition (CVD) offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, excellent transport properties and stable crystalline structure of MoS₂. Despite all the …
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Investigation of MOS-Gated Thyristors and Power Diodes
The MOS-gated thyristors (MGT) refer to the class of power devices that combine the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. The MOS-controlled thyristor (MCT) is a typical MGT device. A comprehensive …
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Hot carrier degradation in deep submicron n-MOS technologies
With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the …
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Optimization and Testing of Nmos Arithmetic Structures (Vlsi, Mos)
Reduction in linewidths in VLSI MOS has a positive effect on the cost/performance of the technology. It both decreases the circuit delays and increases the functionality available on-chip and, as such, gives MOS the potential to become a high performance technology. In order to economically exploit …
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Generation-Recombination Noise in Gold-Doped Silicon Mos Transistors
Made available in DSpace on 2014-12-08T22:24:35Z (GMT). No. of bitstreams: 1 6915424.pdf: 2506667 bytes, checksum: efd71ab4aa16e113e90d49080bfb44d7 (MD5) Previous issue date: 1969
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Thin Oxide MOS Capacitor Studies of Fast Surface States
Submitted by Jesse Garrison (jagarris@illinois.edu) on 2011-07-07T20:53:31Z No. of bitstreams: 1 1971_hunter.pdf: 3687418 bytes, checksum: 4c2047e94e889148dd27584ccd2621a8 (MD5)
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Statistical design of MOS VLSI circuits with designed experiments
Many methods for the statistical design and analysis of integrated circuits have been proposed over the past years. However, these methods typically require a large number of computationally expensive circuit simulator runs, and their applications are limited to small circuits.
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