Functional models for MOS VLSI circuits

In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design applications for VLSI circuits is considered. A method for the automatic generation of functional models for switch- and gate-level circuits is presented. In addition, the use of these models is considered in four CAD applications: switch-level simulation, verification of transistor-level circuits, the initializability of synchronous sequential circuits, and Boolean matching.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Wehbeh, Jalal Anis

Contributors dc:contributor

• Saab, Daniel G.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1994 Wehbeh, Jalal Anis

Language dc:language

eng

Identifier

AAI9512591
(UMI)AAI9512591

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21111