Optimum gate arrangements for MOS standardized layouts

Optimization of size is an important topic of research in the engineering of digital circuits. The field effect transistor (FET) is making an important contribution in this area. In this paper, the basic properties of the FET which pertain to digital circuits will be examined. The problems associated with the physical layout of large integrated circuits using FETs will also be discussed and a standardized method of layout will be reviewed. A simple procedure for optimizing chip area when using this standardized layout method will be developed and illustrated.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2013

Author dc:creator

• Robbins, David H.

Contributors dc:contributor

• Mayeda, Watura

• Field Effect Transistor (FET)

Statement dc:rights

• Copyright 1975 David H. Robbins

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/45707

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/45707