Fast timing simulation of MOS VLSI circuits

The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Overhauser, David Vincent

Contributors dc:contributor

• Hajj, Ibrahim N.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1989 Overhauser, David Vincent

Language dc:language

eng

Identifier

AAI9010975
(UMI)AAI9010975

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19326