{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/19326"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/19326","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Fast timing simulation of MOS VLSI circuits","abstract":"The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.","abstract_html":"The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.","abstract_has_math":false,"creators":["Overhauser, David Vincent"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Hajj, Ibrahim N."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T12:03:59Z","date_published":"2011-05-07T12:03:59Z","updated_at":"2026-07-22T22:25:12Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1989 Overhauser, David Vincent"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9010975","(UMI)AAI9010975"],"render_values":[{"text":"AAI9010975","href":null,"code":true},{"text":"(UMI)AAI9010975","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/19326","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hajj, Ibrahim N."]},{"key":"dc:creator","label":"Author","values":["Overhauser, David Vincent"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T12:03:59Z","10000-01-01","1989"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1989 Overhauser, David Vincent"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9010975","(UMI)AAI9010975","http://hdl.handle.net/2142/19326"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.","Made available in DSpace on 2011-05-07T12:03:59Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9010975.pdf: 6365252 bytes, checksum: e1420d28dde3040d72a2a77e06a415de (MD5) Previous issue date: 1989","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:36:11Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:14:32-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Fast timing simulation of MOS VLSI circuits"]}]}],"canonical_facts":{"dc:contributor":["Hajj, Ibrahim N."],"dc:creator":["Overhauser, David Vincent"],"dc:date":["2011-05-07T12:03:59Z","10000-01-01","1989"],"dc:description":["The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. Verification of the correct operation of VLSI circuits is a very costly process. Therefore, the development of faster verification tools is very important. Fast timing simulation attempts to extract information comparable to that of circuit simulation while requiring processing time comparable to that of logic simulation. This goal is achieved by the use of a nonlinear macromodeling which applies simple voltage calculations with accurate results. Macromodel current equations have been derived based on the dc characteristic equations of MOS transistors, capacitive loading effects, and model card parameters. The voltage-time equations remain relatively simple, although many transistor parameters are included. The equations are used to relate the time response of dc-connected subcircuits to the physical parameters of the devices and their interconnection and take into account the input slew rate and loading. The equations have been implemented in a simulator which produces accurate results and is up to three orders of magnitude faster than SPICE2. The application of these techniques to automatic mixed-mode simulation and parallel processing has also been investigated.","Made available in DSpace on 2011-05-07T12:03:59Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9010975.pdf: 6365252 bytes, checksum: e1420d28dde3040d72a2a77e06a415de (MD5) Previous issue date: 1989","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:36:11Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:14:32-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9010975","(UMI)AAI9010975","http://hdl.handle.net/2142/19326"],"dc:language":["eng"],"dc:rights":["Copyright 1989 Overhauser, David Vincent"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Fast timing simulation of MOS VLSI circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:12Z"}