Projection of TaSiOx/In0.53Ga0.47As Tri-gate transistor performance for future Low-Power Electronic Applications

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2017

Author dc:creator

• Saluru, Sarat K.

Chair dc:contributor.committeechair

• Hudait, Mantu K.

Committee members dc:contributor.committeemember

• Asryan, Levon V.
• Jia, Xiaoting

• InGaAs
• III-V
• Metal-Oxide-Semiconductor Field-Effect Transistors
• Fin-Field-Effect Transistors
• Heterogeneous Integration
• Silicon

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

vt_gsexam:12264

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/78028