Scalable High-Level Synthesis for AI accelerator design

Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Ye, Hanchen

Contributors dc:contributor

• Chen, Deming
• Adve, Vikram
• Huang, Jian
• Neuendorffer, Stephen

• High-Level Synthesis (HLS)
• AI Accelerator
• FPGA
• ASIC
• Design Space Exploration (DSE)
• Deep Neural Networks (DNNs)
• Compiler
• Dataflow
• Intermediate Representation (IR)
• MLIR
• Electronic Design Automation (EDA)
• Hardware-Software Co-design
• Large Language Models (LLMs)
• Convolutional Neural Networks (CNNs)

Statement dc:rights

• Copyright 2025 Hanchen Ye

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/129760

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/129760