{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129760"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129760","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Scalable High-Level Synthesis for AI accelerator design","abstract":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01","abstract_has_math":false,"creators":["Ye, Hanchen"],"institution":"University of Illinois Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming","Adve, Vikram","Huang, Jian","Neuendorffer, Stephen"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-05-01","date_published":"2025-05-01","updated_at":"2026-07-22T22:25:05Z","subjects":["High-Level Synthesis (HLS)","AI Accelerator","FPGA","ASIC","Design Space Exploration (DSE)","Deep Neural Networks (DNNs)","Compiler","Dataflow","Intermediate Representation (IR)","MLIR","Electronic Design Automation (EDA)","Hardware-Software Co-design","Large Language Models (LLMs)","Convolutional Neural Networks (CNNs)"],"languages":["en","eng"],"rights":["Copyright 2025 Hanchen Ye"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129760","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming","Adve, Vikram","Huang, Jian","Neuendorffer, Stephen"]},{"key":"dc:creator","label":"Author","values":["Ye, Hanchen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-05-01","2025-05"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["High-Level Synthesis (HLS)","AI Accelerator","FPGA","ASIC","Design Space Exploration (DSE)","Deep Neural Networks (DNNs)","Compiler","Dataflow","Intermediate Representation (IR)","MLIR","Electronic Design Automation (EDA)","Hardware-Software Co-design","Large Language Models (LLMs)","Convolutional Neural Networks (CNNs)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Hanchen Ye"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129760"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01","The student, Hanchen Ye, accepted the attached license on 2025-05-01 at 12:56.","The student, Hanchen Ye, submitted this Dissertation for approval on 2025-05-01 at 13:32.","This Dissertation was approved for publication on 2025-05-01 at 14:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22119 on 2025-10-19 at 19:54:49","The growing scale and complexity of deep neural networks (DNNs) present significant challenges for efficient hardware acceleration. High-Level Synthesis (HLS) has emerged as a promising methodology to enhance design productivity for FPGA- and ASIC-based accelerators. However, existing HLS workflows struggle to scale effectively due to their inability to address cross-stack co-design challenges spanning architecture design, compiler infrastructure, and Electronic Design Automation (EDA) algorithms. This dissertation proposes a comprehensive and scalable HLS methodology for AI accelerator design by innovating across three synergistic levels. At the design level, we present HybridDNN and DNNExplorer, two frameworks that facilitate the generation and exploration of hardware accelerators through algorithm-aware modeling and fine-grained design space exploration. At the compiler level, we develop ScaleHLS, HIDA, and StreamTensor, which together form a scalable HLS compiler stack that supports multi-level intermediate representations, design space optimizations, and hardware-aware scheduling for both generic and dataflow-based accelerators. At the EDA level, we introduce ISDC, an iterative scheduling algorithm that integrates feedback from downstream tools to significantly enhance resource utilization. Collectively, these contributions constitute a full-stack solution to scalable HLS, advancing the productivity, performance, and adaptability of AI accelerator design."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Scalable High-Level Synthesis for AI accelerator design"]}]}],"canonical_facts":{"dc:contributor":["Chen, Deming","Adve, Vikram","Huang, Jian","Neuendorffer, Stephen"],"dc:creator":["Ye, Hanchen"],"dc:date":["2025-05-01","2025-05"],"dc:description":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01","The student, Hanchen Ye, accepted the attached license on 2025-05-01 at 12:56.","The student, Hanchen Ye, submitted this Dissertation for approval on 2025-05-01 at 13:32.","This Dissertation was approved for publication on 2025-05-01 at 14:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22119 on 2025-10-19 at 19:54:49","The growing scale and complexity of deep neural networks (DNNs) present significant challenges for efficient hardware acceleration. High-Level Synthesis (HLS) has emerged as a promising methodology to enhance design productivity for FPGA- and ASIC-based accelerators. However, existing HLS workflows struggle to scale effectively due to their inability to address cross-stack co-design challenges spanning architecture design, compiler infrastructure, and Electronic Design Automation (EDA) algorithms. This dissertation proposes a comprehensive and scalable HLS methodology for AI accelerator design by innovating across three synergistic levels. At the design level, we present HybridDNN and DNNExplorer, two frameworks that facilitate the generation and exploration of hardware accelerators through algorithm-aware modeling and fine-grained design space exploration. At the compiler level, we develop ScaleHLS, HIDA, and StreamTensor, which together form a scalable HLS compiler stack that supports multi-level intermediate representations, design space optimizations, and hardware-aware scheduling for both generic and dataflow-based accelerators. At the EDA level, we introduce ISDC, an iterative scheduling algorithm that integrates feedback from downstream tools to significantly enhance resource utilization. Collectively, these contributions constitute a full-stack solution to scalable HLS, advancing the productivity, performance, and adaptability of AI accelerator design."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129760"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Hanchen Ye"],"dc:subject":["High-Level Synthesis (HLS)","AI Accelerator","FPGA","ASIC","Design Space Exploration (DSE)","Deep Neural Networks (DNNs)","Compiler","Dataflow","Intermediate Representation (IR)","MLIR","Electronic Design Automation (EDA)","Hardware-Software Co-design","Large Language Models (LLMs)","Convolutional Neural Networks (CNNs)"],"dc:title":["Scalable High-Level Synthesis for AI accelerator design"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:05Z"}