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Showing 1 to 20 of 737 for “"FPGA"”.
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FPGA controlled reconfigurable antenna
… advantages of Field Programmable Gate Arrays (FPGAs) to overcome this dilemma. Two experimental antennas are designed. The first reconfigurable antenna consists of two patches connected by two diodes. The second reconfigurable antenna has sixteen possible combinations and is designed with four …
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FPGA Implementation of Blob Recognition
… has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit …
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FPGA Based Matrix Multiplication Accelerator
… design on the Field Programmable Gate Array (FPGA), which accelerates the matrix dimensions from 2 × 2 to 32 × 32 with elements represented by 8, 16, and 32-bits utilizing the FCSD approach and pipeline structure. All design and simulation are performed using Xilinx Vivado ML edition 2023.2 …
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FPGA-based DOCSIS upstream demodulation
… in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of …
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FPGA based Uniform Channelizer Implementation
… in this thesis, we implement these designs on a FPGA board for the sake of the comprehensive evaluation of resource usage, performance and frequency response. The uniform filter-banks are one of the most essential unit in channelization. The Generalised Discrete Fourier Transform Modulated Filter …
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Přenosy rastrových dat v FPGA
… komunikačních rozhraní na čipu FPGA a jejich využítím pro zpracování a přenos rastrových dat. V implementační části bylo vytvořeno koncové zařízení PCI Express, které zajišťuje přenos dat mezi čipem PFGA a RAM pamětí počítače. Jako zdroj obrazových dat pro zpracování byla k FPGA …
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Python based FPGA design-flow
… of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and …
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A Device-Level FPGA Simulator
In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many …
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GROK-FPGA: Generating Real on-Chip Knowledge for FPGA Fine-Grain Delays Using Timing Extraction
… the other hand, reconfigurable circuits, such as FPGAs, can use more fine-grained, aggressive techniques that carefully choose which resources to use in order to mitigate variation. Knowing which resources to use and avoid, however, requires measurement of underlying variation. We present Timing …
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Timing Driven Analytical Placement for FPGA
… Annealing (SA) based placement methods for FPGAs give best results in terms of wirelength and critical path delay. The runtime for these SA based methods is directly proportional to the total number of cells to be placed. In case of modern multi-million gate FPGAs, SA based methods for …
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FPGA acceleration of DNA error correction
… large genomes. The thesis describes the first FPGA-based error-correction tool, which is designed to improve the throughput of DNA error correction for Illumina reads. The base algorithm of the FPGA implementation is BLESS which is highly accurate but slow. The hardware implemented on the FPGA …
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CAD for a 3-dimensional FPGA
… fabrication of Field Programmable Gate Arrays (FPGAs) are analyzed. A CAD tool has been developed to specify 3-dimensional FPGA architectures and map RTL descriptions of circuits to these 3-D FPGAs. The CAD tool was created from the widely used Versatile Place and Route (VPR) CAD tool for 2-D …
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Design of a 3-dimension FPGA
… of 3-D integration on the delay and power of FPGA chips is analyzed. Different physical partitioning of FPGAs is proposed for 3-D integration and one is analyzed in detail. The size of 3-D FPGAs differs from the size of 2-D FPGAs because of the overhead of 3-1D connections and different …
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FPGA-aided MAV vision-based estimation
… containing a Field-Programmable-Gate-Array (FPGA). Most implementations using a monocular camera onboard MAVs stream images to a ground station for processing. However, an FPGA can be programmed for feature extraction, so instead of sending raw images, information is encoded by the FPGA and …
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An FPGA-based Target Acquisition System
… algorithm are compared side-by-side in an FPGA-based test platform. Results show that although the strictly hardware implementation leads in terms of lower power consumption and very low area consumption, modification of and programming for the multi-core software implementation is simpler …
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Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS
… die Konzeption und Realisierung des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS als Triggerprozessor für das geplante ATLAS-Experiment am CERN. Auf der Basis von CompactPCI wird eine enge Verknüpfung zwischen einem Multi-FPGA-System und einer Standard-CPU umgesetzt. Das System ist in …
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DCD Algorithm: Architectures, FPGA Implementations and Applications
… architectures and field-programmable gate array (FPGA) implementations of two variants of the DCD algorithm, known as the cyclic and leading DCD algorithms, for real-valued and complex-valued systems. For each of these techniques, we present architectures and implementations with different degree …
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SIMD pipelined processor implemented on a FPGA
… board that contains Xilinx Virtex II Pro XC2VP30 FPGA, package FF896. The maximum number of units that can be instantiated in the FPGA on the XUP board is eight units which would use the entire FPGA slice area. This allows the processor to complete eight sets of 32-bit data operations per cycle …
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FPGA-based implementation of parallel graph partitioning
… multiprocessor system is implemented on an FPGA. The system designed provides a cost-effective solution. The design is based on two Altera soft IP Nios processors. They are synchronized using shared locks. Also, they communicate information by writing messages into buffers. These buffers are …
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Detekce obsazenosti rádiového kanálu v obvodu FPGA
… metod a implementace vybrané metody do obvodu FPGA
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