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Showing 1 to 20 of 165 for “"ASIC"”.

  1. Fair Comparison of ASIC Performance for SHA-3 Finalists

    … on hardware has made implementations on ASIC benchmarks extremely important. Although all kinds of secure algorithms have been implemented into various devices, the effects from different constraints on ASIC implementation performance have never been explored before. In order to analyze …

    vt Repository record for Fair Comparison of ASIC Performance for SHA-3 Finalists (opens in a new tab)

  2. Design and analysis of an ASIC for energy harvesting applications

    … create a steady dc output voltage of 4.1 V. The ASIC for this system was designed using 0.6μm complementary metal-oxide-semiconductor (CMOS) technology.

    tdl Repository record for Design and analysis of an ASIC for energy harvesting applications (opens in a new tab)

  3. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology

    … This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, …

    calpoly Repository record for Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology (opens in a new tab)

  4. ALA ASIC : a standard cell library for Asynchronous Logic Automata

    … mapping from software to hardware. Included are basic design tools to enable writing ALA software, the necessary hardware designs for implementation, and simulation techniques for quickly verifying correctness and performance. This thesis also documents many of the hazards and opportunities for …

    mit Repository record for ALA ASIC : a standard cell library for Asynchronous Logic Automata (opens in a new tab)

  5. Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development

    … Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design …

    vt Repository record for Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development (opens in a new tab)

  6. Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices

    Portable DNA sequencing, particularly using nanopore technology, has the potential to revolutionize genomics by making it accessible in a wide range of environments. However, current state-of-the-art devices face significant challenges due to the lack of integrated bioinformatics processing …

    york Repository record for Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices (opens in a new tab)

  7. Charakterisierung und Entwicklung eines CIP-Auslese-ASIC für das H1-Upgrade-Projekt 2000

    … Der CIPix wurde im Rahmen dieser Diplomarbeit im ASIC-Labor der Universität Heidelberg entwickelt und wird als Auslesechip für das CIP-Upgrade- Projekt eingesetzt werden. Er besteht aus 64 ladungsempfindlichen, rauscharmen Vorverstärkern. Die verstärkten Signale werden von 64 Komparatoren mit …

    heid-thes Repository record for Charakterisierung und Entwicklung eines CIP-Auslese-ASIC für das H1-Upgrade-Projekt 2000 (opens in a new tab)

  8. Entwicklung einer Testumgebung für einen ASIC im Rahmen des ATLAS L-1-Triggers

    … einem Application Specific In- tegrated Circuit (ASIC) zu implementieren. Dieser erhält Eingangsdaten vom Ka- lorimeter mit einer Datenrate von 800 Mbit/s. Die vorliegende Diplomarbeit hatte zum Ziel, einen Test-ASIC (TASIC), der eine Vorstufe zum Triggerprozessor-ASIC darstellt, zu testen. Wie …

    heid-thes Repository record for Entwicklung einer Testumgebung für einen ASIC im Rahmen des ATLAS L-1-Triggers (opens in a new tab)

  9. A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

    This work presents a scalable Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasound. It leverages programmable electronic addressing to achieve linear scaling for both hardware interconnection and software data acquisition. A 16x16 transceiver ASIC is fabricated and …

    mit Repository record for A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging (opens in a new tab)

  10. Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

    The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) …

    unlv Repository record for Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification (opens in a new tab)

  11. The adoption of Application Specific Integrated Circuit (ASIC) technology by the UK manufacturing base

    … Define Application Specific Integrated Circuit (ASIC) technology and review its history • Review that nature of the UK SME base and identify why they should use ASICs • Review the UK, European and World ASIC markets • Analyse the nature of the UK ASIC design and supply industry • Ascertain the …

    the-open-u Repository record for The adoption of Application Specific Integrated Circuit (ASIC) technology by the UK manufacturing base (opens in a new tab)

  12. Protonenempfindlichkeit von Spinalganglienneuronen bei Wildtypmäusen und Mausmutanten mit einem Mangel an TRPV 1 oder ASIC 3

    … diesem Zusammenhang entdeckten Kanälen TRPV1 und ASIC3 auf die Protonensensitivität von nativen Spinalganglienneuronen, sowie Unterschiede zwischen der IB4-positiven und der IB4-negativen Population untersucht. Hierzu wurden Patch-Clamp-Studien an isolierten Neuronen von TRPV1-defizienten und …

    wurz-thes Repository record for Protonenempfindlichkeit von Spinalganglienneuronen bei Wildtypmäusen und Mausmutanten mit einem Mangel an TRPV 1 oder ASIC 3 (opens in a new tab)

  13. The Design of an Asic Control Chip for a Forward Active Clamp Converter and the Investigation of Integratable Lateral Power Devices

    In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog …

    vt Repository record for The Design of an Asic Control Chip for a Forward Active Clamp Converter and the Investigation of Integratable Lateral Power Devices (opens in a new tab)

  14. Signal Conditioning Circuits for Injectable Pressure Sensors

    … this level is only possible through creating an ASIC which includes all functions to allow sensor readout, power reception and data transfer. This work investigated a low-power, injectable pressure sensor readout ASIC in a 180 nm CMOS process to support injectable capacitive pressure sensors. The …

    auckland-ms Repository record for Signal Conditioning Circuits for Injectable Pressure Sensors (opens in a new tab)

  15. ACID-SENSING ION CHANNELS: TARGETS FOR NEUROPEPTIDE MODULATION AND NEURONAL DAMAGE

    Acid-sensing ion channels (ASICs) are proton-gated channels expressed in neurons in the central and peripheral nervous systems. These ion channels are sensors for extracellular pH and contribute to a variety of normal functions including learning and memory, seizure termination, fear, anxiety, and …

    ohiolink Repository record for ACID-SENSING ION CHANNELS: TARGETS FOR NEUROPEPTIDE MODULATION AND NEURONAL DAMAGE (opens in a new tab)

  16. High level behavioural modelling of boundary scan architecture.

    … Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion …

    bournemouth Repository record for High level behavioural modelling of boundary scan architecture. (opens in a new tab)

  17. Extensible Real-Time Sensor and Test Interface for a System-on-Chip

    … custom Application-Specific Integrated Circuit (ASIC). The ASIC, previously developed by the Low-Energy Autonomy and Navigation research group, is designed for autonomous navigation on microrobots, such as drones. To enable the real-time data processing required for this application, the ASIC

    mit Repository record for Extensible Real-Time Sensor and Test Interface for a System-on-Chip (opens in a new tab)

  18. Secure and Efficient Implementations of Cryptographic Primitives

    … cross-platform comparison between SHA-3 FPGA and ASIC benchmarking results and propose a methodology for lightweight hash designs. Finally, we provide guidelines to select implementation attack countermeasures in ECC cryptosystem designs. We discuss how to integrate a set of countermeasures to …

    vt Repository record for Secure and Efficient Implementations of Cryptographic Primitives (opens in a new tab)

  19. Investigation of Non-Traditional Applications of the Physical Level in Reconfigurable Computing

    … and Application Specific Integrated Circuit (ASIC) design processes to enable additional research avenues. In order to accomplish these projects, Tools for Open Reconfigurable Computing (TORC) is utilized to provide a robust environment for circuit analysis and modifications. These projects …

    vt Repository record for Investigation of Non-Traditional Applications of the Physical Level in Reconfigurable Computing (opens in a new tab)

  20. Developing digital and analog spiking neural Networks for interacting with biological Tissues in the Case Study of temporal lobe Epilepsy

    … to the costly and time-intensive process of ASIC chip design. Experimental results demonstrated the capability of the SNN to learn and adapt using Spike-Timing-Dependent Plasticity (STDP) algorithms, laying the foundation for further hybrid experiments conducted with the IIT team. Subsequent …

    sevilla Repository record for Developing digital and analog spiking neural Networks for interacting with biological Tissues in the Case Study of temporal lobe Epilepsy (opens in a new tab)

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