A jittered-sampling correction technique for ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.

Grantor dc:publisher

Edith Cowan University, Research Online, Perth, Western Australia

Year dc:date

2008

Author dc:creator

• Tourabaly, Jamiil A.

• Jitter
• ADC
• flicker noise
• phase noise
• Passive CMOS
• Computer Engineering

Repository record dc:identifier

https://ro.ecu.edu.au/theses/27

OAI identifier oai:identifier

oai:ro.ecu.edu.au:theses-1027