Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 256 for “"Jitter"”.
-
Asynchronous data-dependent jitter compensation
Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. …
-
Techniques for low jitter clock multiplication
… Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit …
-
Analysis and Design of Low-Jitter Oscillators
This thesis presents an examination of the jitter performance of different oscillator types in the presence of flicker noise, white noise and power supply noise. Key results are achieved using time domain simulations to determine cycle jitter of several different oscillator architectures, …
-
Timing jitter studies in modelocked fiber lasers
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
-
A sampling jitter tolerant continuous-time pipeline ADC
A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling …
-
The control of a high-speed, low-jitter pulse generator
Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1986
-
Low jitter phase-locked loop clock synthesis with wide locking range
… applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications …
-
A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
… ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. …
-
Low-jitter symbol timing recovery for M-ary QAM and PAM signals
This thesis focuses on low-jitter symbol timing recovery schemes applicable to M-ary QAM and PAM signals. Franks and Bubrowski introduced highpass prefiltering and symmetric bandpass post-filtering for jitter-free operation of a symbol timing recovery scheme using a squarer for binary signaling. We …
-
Attosecond timing jitter modelocked lasers and ultralow phase noise photonic microwave oscillators
… output peak power over previous results. Timing jitter of 1 00-MHz Cr:LiSAF lasers is measured with a single-crystal balanced optical cross-correlator to be -30 as from 10 kHz to 50 MHz. Pump intensity noise coupled into phase noise through the self-steepening effect proves to be the major noise …
-
Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. …
-
Characterization of channel simulation method with Jitter and equalization effect on eye diagram
… The eye diagram representation involving the jitter and equalization on both the transmitter and receiver ends is considered.
-
Analysis and characterization of random skew and jitter in a novel clock network
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
-
(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
… the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This …
-
A low-skew, low jitter receiver circuit for on-chip optical clock distribution
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
-
Laser scanner jitter characterization, page content analysis for optimal rendering, and understanding image graininess
… office copiers. In the EP process, laser scanner jitter is a common artifact that mainly appears along the scan direction due to the condition of polygon facets. Prior studies have not focused on the periodic characteristic of laser scanner jitter in terms of the modeling and analysis. This …
-
Femtosecond fiber lasers at 1550 nm for high repetition rates and low timing jitter
… pulse widths, and sub 10 femtosecond timing jitters. This thesis describes the design, fabrication, and characterization of three different iterations of mode-locked laser sources utilizing erbium doped fibers and semiconductor saturable absorbing mirrors to form pulse trains in the 1550 nm …
Page 1 of 13