Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 330 for “"ADC"”.
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Precision hybrid pipelined ADC
… to single-ended and differential pipelined ADCs, with effective number of bits (ENOB) ranging from 8 bits to 11 bits at sampling rates from 10MS/s to 100MS/s. The purpose of this project was to explore the use of the ZCBC technique for high-precision ADCs. The goal of the project is a 13-bit …
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A SEIR-based ADC built-in-self-test and its application in ADC self-calibration
… DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and …
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Custom High-Speed ADC for mmWave Digital Beamformers
… and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality …
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Low-power SAR ADC for biomedical portable devices
… (SAR) Analog to Digital Converters (ADCs) stand out as the preferred choice for such applications due to their remarkable energy efficiency and nearly digital architecture. The SAR architecture’s scalability allows for energy consumption optimisation across a broad spectrum of …
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Variable Precision Tandem Analog-to-Digital Converter (ADC)
… proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the …
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A 1.7GS/s SAR ADC in 28nm CMOS
… thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for increasing …
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Equation-based hierarchical optimization of a pipeline ADC
… optimizations of a 10-stage pipeline ADC in a 0.18-um process. A pipeline ADC was chosen because it is a system small enough to be handled by a flat optimization, yet large enough to be approached with a hierarchical methodology. This allows a quantitative comparison of the computation …
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A sampling jitter tolerant continuous-time pipeline ADC
… jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock …
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ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC
… (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both …
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A highly digital, reconfigurable and voltage scalable SAR ADC
… reconfigurable analog-to-digital converter (ADC) is needed to digitize a wide range of signals with varying bandwidth and resolution requirements. This thesis describes the design of an ADC whose power scales exponentially with resolution and linearly with frequency to maximize the system …
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SHA-less pipeline ADC design with sampling clock skew calibration
… of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline …
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An ultra low power ADC for wireless micro-sensor applications
… an ultra low-power analog-to-digital converter (ADC) whose sampling rate and resolution can be scaled to dynamically recover power savings. The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either 12 or 8 bits. The design is based on the successive approximation register …
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Optimizing communication performance of low-resolution ADC systems with hybrid beamforming
Low-resolution analog-to-digital converter (ADC) systems and hybrid analog-and-digital beamforming systems have drawn extensive attention as a promising receiver architecture for millimeter wave (mmWave) communications by reducing hardware cost and power consumption. In this dissertation, hybrid …
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Low-power high-performance SAR ADC design with digital calibration techniques
… (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the …
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A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
… systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In …
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An on-chip input driver for a high-voltage SAR ADC
… design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the driver …
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Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC
… is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction …
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Cmos Design of an 8-Bit 1MS/S Successive Approximation Register ADC
… of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.</p> <p>This thesis presents an 8-bit successive approximation …
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