Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic

<p>As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture. </p>

Name thesis:degree_name

Master of Science in Computer Engineering (MSCmpE)

Level thesis:degree_level

Thesis

Year dc:date.available

2019

Author dc:creator

• Mize, Nicholas Renoudet

Advisor dc:contributor.advisor

• Di, Jia

Contributors dc:contributor

• Thompson, Dale R.

• Asynchronous
• Circuit
• Digital
• MTNCL
• Synthesis
• VHDL
• Digital Circuits
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/3168

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-4718