As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.
","abstract_html":"<p>As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture. </p>","abstract_has_math":false,"creators":["Mize, Nicholas Renoudet"],"institution":null,"degree_name":"Master of Science in Computer Engineering (MSCmpE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Thompson, Dale R."],"advisors":["Di, Jia"],"committee_chairs":[],"committee_members":[],"year":2019,"date_issued":"2019-05-01T07:00:00Z","date_published":"2019-05-01T07:00:00Z","updated_at":"2026-07-24T00:59:24Z","subjects":["Asynchronous","Circuit","Digital","MTNCL","Synthesis","VHDL","Digital Circuits","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/3168","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Di, Jia","Thompson, Dale R."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Di, Jia"]},{"key":"dc:creator","label":"Author","values":["Mize, Nicholas Renoudet"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2019"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2024-02-06T08:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Computer Engineering (MSCmpE)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Asynchronous","Circuit","Digital","MTNCL","Synthesis","VHDL","Digital Circuits","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/3168"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.
"]},{"key":"dc:title","label":"Title","values":["Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic"]}]}],"canonical_facts":{"dc:contributor":["Di, Jia","Thompson, Dale R."],"dc:contributor.advisor":["Di, Jia"],"dc:creator":["Mize, Nicholas Renoudet"],"dc:date":["2019"],"dc:date.available":["2024-02-06T08:00:00Z"],"dc:description.abstract":["As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.
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