Global ETD Search

Clock tree synthesis under aggressive buffer insertion

Chen, Ying-YuUniversity of Illinois at Urbana-Champaign2012

In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer …

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Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic

Mize, Nicholas Renoudet2024

… designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement …

arkansas Repository record for Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic (opens in a new tab)

Spatial and Temporal Scheduling of Clock Arrival Times for IR Hot-Spot Mitigation, Reformulation of Peak Current Reduction & Physical Design Automation Tool

Gunna, Bhoopal

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