Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 155 for “"VHDL"”.
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Parallel Algorithms for VHDL Simulation
We finally settled on a partitioning based approach to parallelization. This technique gives us acceptable speedups, if the partitioning and placement of partitions on processors is done carefully. Partitioning and placement issues are examined thoroughly in this thesis.
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Automatic verification of VHDL models
… A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has been proposed. In the proposed scheme the specifications for the hardware system, i.e.,the timing constraints and relations between input and output signals are described by the designer in …
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Timing distribution in VHDL behavioral models
… enables the use of imbedded timing in behavioral VHDL models, thereby providing accurate VHDL descriptions. Due to this modeling methodology, the end-to-end delays for all the paths in the digital device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is …
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Methodology for structured VHDL model development
… this thesis describes the development of VHDL primitives supporting digital signal processing (DSP) and image processing operations for two of the RASSP specific applications: 1) Synthetic aperture radar image processor (SAR) and 2) Automatic target recognition (ATR) image processing …
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A graphical representation for VHDL models
… graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process …
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A framework for synthesis from VHDL
… system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key …
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Rapid development of VHDL behavioral models
… Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's …
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Board level diagnosis techniques using VHDL modeling
… The program uses information from a non-faulted VHDL model of the board to learn what to expect. Since there is no interface to a real probed board, VHDL is also used to model the faulted board.
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Hierarchical test generation for VHDL behavioral models
… several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed …
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Mapping conceptual graphs to primitive VHDL processes
… for mapping conceptual graphs to primitive VHDL processes. The behavior of each primitive process is stored in the form of a schema. The algorithm identifies concepts in the input referring to MODAS (Modeler's Assistant) process primitives and maps their schemata to the input conceptual …
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Behavior modeling of RF systems with VHDL
Behavioral modeling of RF systems with VHDL is considered and a modeling methodology is developed for modeling the I/O response of these systems. A Pulsed Doppler radar system is chosen as a representative system, and a VHDL model for this system is presented. The modeling approach and the working …
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Modeling SAR signals and sensors using VHDL
… data. If the signal processor is modeled in VHDL then the sequence of sensor data will be applied to the model in a VHDL test bench. Generation of the sensor data and sensor models for VHDL testbenches is a labor intensive task which cannot be performed manually. This thesis concentrates on …
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Hardware modeling and top-down design using VHDL
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991.
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Process level test generation for VHDL behavioral models
… (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL …
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Methodology for VHDL performance model construction and validation
… in the development of a methodology to construct VHDL performance models which will help to significantly reduce the time from an initial conception to a working design. To further reduce development time, reuse of existing structural primitives is emphasized. Typical models of multi-processor …
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Natural language interface to a VHDL modeling tool
… describes a Natural Language (NL) interface to a VHDL modeling tool called the Modeler's Assistant. The primary motivation for the interface developed in this research work is to permit VLSI modelers who are not proficient in VHDL to rapidly produce correct VHDL models from manufacturer's …
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Interfacing VHDL performance models to algorithm partitioning tools
… a set of tools that directly interfaces the VHDL performance models to the algorithm partitioning tools will significantly reduce the time and effort needed to prepare the various models. In order to develop the interface tools, it is essential to determine the information that needs to be …
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