A graphical representation for VHDL models

This paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers. *VHDLCad is a trademark of David G. Burnette. **Copyright 1988 by David G. Burnette. All rights reserved

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1988

Author dc:creator

• Burnette, David G.

Chair dc:contributor.committeechair

• Armstrong, James R.

Committee members dc:contributor.committeemember

• Tront, Joseph G.
• Ha, Dong Sam

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-06222010-020057

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43381