Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 35 for “"Fault Simulation"”.
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Test analysis & fault simulation of microfluidic systems
This work presents a design, simulation and test methodology for microfluidic systems, with particular focus on simulation for test. A Microfluidic Fault Simulator (MFS) has been created based around COMSOL which allows a fault-free system model to undergo fault injection and provide test …
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Architectural Level Test Generation and Fault Simulation
In this thesis, a high level branch-and-bound based ATPG approach will be first presented. This method is a reasonable extension of the gate level ATPG approaches. Although various effective techniques have been applied, this method has sluggish performance for circuits with complicated data path …
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Parallel hardware accelerated switch level fault simulation
Switch level faults, as opposed to traditional gate level faults, can more accurately model physical faults found in an integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n²), where n is the number of devices in the circuit. This paper …
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Functional level fault simulation of LSI devices
Procedures for the modeling and simulation of faults in LSI devices at functional level are developed. Generalized functional level fault classes are defined for digital LSI devices such as microprocessor and peripheral chips. General procedures to inject functional level faults in the LSI chip …
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Parallel algorithms for test generation and fault simulation
… it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using …
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Fault simulation for structural testing of analogue integrated circuits
In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by …
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Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
All implementations were done using the MPI communication library and are therefore portable to many parallel platforms. All algorithms provide excellent performance in terms of speedup and quality on both shared-memory and distributed-memory parallel platforms.
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Automatic generation of high level fault simulation models for analogue circuits
… (AMG) approaches. Furthermore, high level fault modelling (HLFM) has been shown to work reasonably well using manually designed fault models. However, no evidence shows that published AMG approaches based on op amps have been used in HLFM.This thesis describes an investigation into the …
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Use of High-Level Descriptions in Fault Simulation and Test Generation
… advantage of using functional descriptions for fault simulation and test generation. By using functional descriptions, high-level functional modules are treated as circuit primitives, as compared with low-level gates and flip-flops which are used in conventional approaches, and the number of …
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On fault coverage and fault simulation for multiple signature analysis BIST schemes
Fault coverage and fault simulation issues related to multiple signature analysis (MSA) built-in self-test (BIST) schemes are treated here. A model to predict the fault coverage is presented. Based on this model, the nature of the fault coverage for MSA is discussed. The fault coverage of MSA is a …
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On improving the performance of parallel fault simulation for synchronous sequential circuits
… that aim to improve the performance of parallel fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of …
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Fault simulation for supply current testing of bridging faults in CMOS circuits
… is to develop and implement a method for fault simulation that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level …
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Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits
In this dissertation, we propose two fault simulators, called HOPE and HOPE2, and an autolllatic test pattern generator (ATPG), called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
Fault collapsing, test generation, and fault simulation were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the …
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The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Embargo set by: Seth Robbins for item 69555 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs
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A gate-level simulator for alpha-particle-induced transient faults
… for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of …
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Symbolic methods for testing digital circuits
… circuits at gate level. <br>Both major topics, fault simulation and automated test pattern generation (ATPG), have been examined, among others, like build-in self-test, computing reset sequences for a sequential circuit, identifying uninitializable memory elements, or computing approximations …
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Multi-processor logic simulation at the chip level
… parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. …
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Simulation-based techniques for sequential circuit testing
Fault simulators are used extensively in the design of electronic circuits for both testing and fault diagnosis. Complex component types can be easily handled in a fault simulator, since processing occurs in the forward direction only, and various fault models can be accommodated. This research is …
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Simulation- and Deduction-Based Techniques for Fault Diagnosis
… dynamic processing for the diagnosis of bridging faults in sequential circuits is presented. During diagnosis, the failing outputs from the test are used to adaptively determine the behavior of the bridge at each time-frame. Selective faulty state information is stored by performing accurate …
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