Functional level fault simulation of LSI devices

Procedures for the modeling and simulation of faults in LSI devices at functional level are developed. Generalized functional level fault classes are defined for digital LSI devices such as microprocessor and peripheral chips. General procedures to inject functional level faults in the LSI chip models are illustrated with the help of various examples. Next, techniques of automating the simulation of the faulty systems are discussed. Finally, simulation of faults at the functional level is compared with the gate level simulation in case of INTEL 8212 (8 bit I/O) chip.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1982

Author dc:creator

• Sathe, Shirish K.

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/10919/88557

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/88557