A gate-level simulator for alpha-particle-induced transient faults

Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Cha, Hungse

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1994 Cha, Hungse

Language dc:language

eng

Identifier

AAI9512321
(UMI)AAI9512321

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/23457