{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/23457"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/23457","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A gate-level simulator for alpha-particle-induced transient faults","abstract":"Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.","abstract_html":"Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.","abstract_has_math":false,"creators":["Cha, Hungse"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Engineering, Electronics and Electrical","degree_department":null,"school":null,"contributors":["Patel, Janak H."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T14:14:53Z","date_published":"2011-05-07T14:14:53Z","updated_at":"2026-07-22T22:25:22Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1994 Cha, Hungse"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9512321","(UMI)AAI9512321"],"render_values":[{"text":"AAI9512321","href":null,"code":true},{"text":"(UMI)AAI9512321","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/23457","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Patel, Janak H."]},{"key":"dc:creator","label":"Author","values":["Cha, Hungse"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T14:14:53Z","10000-01-01","1994"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering, Electronics and Electrical"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1994 Cha, Hungse"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9512321","(UMI)AAI9512321","http://hdl.handle.net/2142/23457"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.","Using this simulator, benchmark circuits have been tested for their behavior under alpha-particle injections. The experiments show that the one bit flip model is not a good model for injecting faults in highly fault tolerant systems. The experiments also show that at the pin level, no simple model exists which can mimic the behavior of the circuit hit with alpha particles.","The simulator's usefulness is also shown in the development of a transient pulse tolerant D flip-flop (DFF). The tool is used to demonstrate the tradeoff between transient pulse tolerance and latch performance.","Made available in DSpace on 2011-05-07T14:14:53Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9512321.pdf: 3252970 bytes, checksum: ba5f9b6ae40a827b31548dc93de511b7 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:04:36Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:30:53-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["A gate-level simulator for alpha-particle-induced transient faults"]}]}],"canonical_facts":{"dc:contributor":["Patel, Janak H."],"dc:creator":["Cha, Hungse"],"dc:date":["2011-05-07T14:14:53Z","10000-01-01","1994"],"dc:description":["Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.","Using this simulator, benchmark circuits have been tested for their behavior under alpha-particle injections. The experiments show that the one bit flip model is not a good model for injecting faults in highly fault tolerant systems. The experiments also show that at the pin level, no simple model exists which can mimic the behavior of the circuit hit with alpha particles.","The simulator's usefulness is also shown in the development of a transient pulse tolerant D flip-flop (DFF). The tool is used to demonstrate the tradeoff between transient pulse tolerance and latch performance.","Made available in DSpace on 2011-05-07T14:14:53Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9512321.pdf: 3252970 bytes, checksum: ba5f9b6ae40a827b31548dc93de511b7 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:04:36Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:30:53-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9512321","(UMI)AAI9512321","http://hdl.handle.net/2142/23457"],"dc:language":["eng"],"dc:rights":["Copyright 1994 Cha, Hungse"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["A gate-level simulator for alpha-particle-induced transient faults"],"dc:type":["text"],"thesis:degree_discipline":["Engineering, Electronics and Electrical"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:22Z"}