Architectural Level Test Generation and Fault Simulation

In this thesis, a high level branch-and-bound based ATPG approach will be first presented. This method is a reasonable extension of the gate level ATPG approaches. Although various effective techniques have been applied, this method has sluggish performance for circuits with complicated data path or control. The second approach, based on a nonlinear equation solving, is proposed to overcome the difficulties. The test generation process is separated into two phases. An instruction sequence assembling methodology is developed in the first phase to search for a valid instruction sequence for the injected test vector of the module under test. In the second phase, a complete system of nonlinear equations is derived based on the instruction sequence, and a discrete relaxation algorithm is proposed to solve this system of equations to derive the value solution. In the first phase, only path analysis is performed so that the complexity of searching is significantly reduced. The exact value solution is derived in the second phase and the data flow value conflicts are efficiently solved. The experimental results show that the proposed techniques are very effective and promising.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Lee, Jaushin

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Identifier

(UMI)AAI9305598

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/71982