Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"Design for Testability"”.
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A Design Methodology for Physical Design for Testability
Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in …
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Issues in Design for Testability and Self-Test
This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.
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Design for Testability Techniques to Optimize VLSI Test Cost
… test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test …
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Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips
… biochips constitute an emerging technology for the automation of biochemical procedures. Recent advances in fabrication techniques have enabled the development of these devices. Increasing integration levels provide biochips with tremendous potential; a large number of bioassays, i.e., …
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Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
… have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… alleviate many of these problems, and is therefore viewed as a promising interconnect paradigm of the future. In addition, NOC building blocks consist of reusable components and require minimal design effort in building a large and complex system. In addition to NOCs, 3D integration technology …
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Testing and Fault-Tolerance Aspects of High-Density VLSI Memory
Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of …
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Simulation-based techniques for sequential circuit testing
Fault simulators are used extensively in the design of electronic circuits for both testing and fault diagnosis. Complex component types can be easily handled in a fault simulator, since processing occurs in the forward direction only, and various fault models can be accommodated. This research is …
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High-Level Testability Analysis and Enhancement for Digital Systems
The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a …
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Enhancing testability of VLSI circuits using partial reset techniques
… costs, circuits must be more testable. Several design for testability (DFT) schemes which trade off various design parameters have been proposed towards that end. The primary focus of this research is a technique called partial reset (PR). Rather than allowing all memory elements in a sequential …
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Testing infrastructure and other considerations in a waferscale processor
… scaling, the improvement of computational performance is exploited through parallel computing. Further stimulated by emerging workloads, like machine learning, big data processing, and cloud computing, which are either inherently parallel workloads or easily parallelizable, processor core …
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The testability of regular logic structures
… that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized …
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A cost quality model for CMOS IC design
… requires planning from the initial stage of design. This research proposes a concurrent engineering-based design methodology for layout optimization. The proposed method for layout optimization is iterative, and layout changes in each design iteration are made based on the principles of …
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ATPG and DFT Algorithms for Delay Fault Testing
… a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of …
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Integrated Enhancement of Testability and Diagnosability for Digital Circuits
… test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also …
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Testing and Verification Strategies for Enhancing Trust in Third Party IPs
… has surged up the trend of outsourcing component design and manufacturing process across geographical boundaries. While cost reduction and short time to market are the driving factors behind this trend, the authenticity of the final product remains a major question. Third party deliverables are …
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New techniques for quality and reliability enhancement in electronic systems
L'abstract è presente nell'allegato / the abstract is in the attachment