Enhancing testability of VLSI circuits using partial reset techniques

To reduce total chip production costs, circuits must be more testable. Several design for testability (DFT) schemes which trade off various design parameters have been proposed towards that end. The primary focus of this research is a technique called partial reset (PR). Rather than allowing all memory elements in a sequential circuit to be reset by a primary input, only a subset of them is given the capability to reset. Partial reset can assist in initializing the circuit and in providing additional controllability to the circuit. Partial reset has less hardware overhead and typically smaller test application times than scan design. Partial reset, furthermore, allows unrestricted at-speed testing. The tradeoff is in slightly lower testability. Methods of selecting the flip-flops to be reset and the associated reset values are presented. A scheme utilizing multiple reset lines is shown to raise the controllability in the circuit. A dynamic flip-flop selection method is described utilizing a fast sequential test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements and partial scan into a given circuit. The result is higher fault coverage than is possible with PR alone and faster test application times than scan design.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Mathew, Ben

Contributors dc:contributor

• Saab, Daniel G.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1994 Mathew, Ben

Language dc:language

eng

Identifier

AAI9512479
(UMI)AAI9512479

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20241