High-Level Testability Analysis and Enhancement for Digital Systems

The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Hsu, Frank Fu-Chang

Contributors dc:contributor

• Patel, Janak H.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI9912272

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81267