{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81267"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81267","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"High-Level Testability Analysis and Enhancement for Digital Systems","abstract":"The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.","abstract_html":"The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.","abstract_has_math":false,"creators":["Hsu, Frank Fu-Chang"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Patel, Janak H."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:19Z","date_published":"2015-09-25T20:10:19Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Computer Science"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9912272"],"render_values":[{"text":"(MiAaPQ)AAI9912272","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81267","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Patel, Janak H."]},{"key":"dc:creator","label":"Author","values":["Hsu, Frank Fu-Chang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:19Z","10000-01-01","1998"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81267","(MiAaPQ)AAI9912272"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.","Made available in DSpace on 2015-09-25T20:10:19Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9912272.pdf: 2592551 bytes, checksum: f7eb84571a21db8db38b0620dfdb2fb3 (MD5) Previous issue date: 1998","Embargo set by: Seth Robbins for item 82548 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","91 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998."]},{"key":"dc:title","label":"Title","values":["High-Level Testability Analysis and Enhancement for Digital Systems"]}]}],"canonical_facts":{"dc:contributor":["Patel, Janak H."],"dc:creator":["Hsu, Frank Fu-Chang"],"dc:date":["2015-09-25T20:10:19Z","10000-01-01","1998"],"dc:description":["The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a subset of the variables listed in the high-level description is made fully controllable and observable to maximize the testability grading of the design. Then the registers that correspond to the selected variables are placed onto the scan-chain for partial-scan implementation. Experimental results show that the testability grading does correlate to the actual testability of circuits, and our technique produces partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.","Made available in DSpace on 2015-09-25T20:10:19Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9912272.pdf: 2592551 bytes, checksum: f7eb84571a21db8db38b0620dfdb2fb3 (MD5) Previous issue date: 1998","Embargo set by: Seth Robbins for item 82548 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","91 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998."],"dc:identifier":["http://hdl.handle.net/2142/81267","(MiAaPQ)AAI9912272"],"dc:language":["eng"],"dc:subject":["Computer Science"],"dc:title":["High-Level Testability Analysis and Enhancement for Digital Systems"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:15Z"}