Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

<p>Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. </p> <p>This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL). </p>

Name thesis:degree_name

Doctor of Philosophy in Engineering (PhD)

Level thesis:degree_level

Dissertation

Year dc:date.available

2014

Author dc:creator

• Alibeygi Parsan, Farhad

Advisor dc:contributor.advisor

• Smith, Scott C.

Contributors dc:contributor

• Al-Assadi, Waleed K.
• Di, Jia

• Asynchronous
• MTNCL
• NCL
• NULL Convention Logic
• SCL
• Sleep Convention Logic
• Digital Circuits
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/2119

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-3658