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Virginia Tech

Tensile-Strained Ge/III-V Heterostructures for Low-Power Nanoelectronic Devices

Abstract

dc:description.abstract

The aggressive reduction of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has resulted in an exponential increase in computing power. Stemming from increases in device density and substantial progress in materials science and transistor design, the integrated circuit has seen continual performance improvements and simultaneous reductions in operating power (VDD). Nevertheless, existing Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are rapidly approaching the physical limits of their scaling potential. New material innovations, such as binary group IV or ternary III-V compound semiconductors, and novel device architectures, such as the tunnel field-effect transistor (TFET), are projected to continue transistor miniaturization beyond the Si CMOS era. Unlike conventional MOSFET technology, TFETs operate on the band-to-band tunneling injection of carriers from source to channel, thereby resulting in steep switching characteristics. Furthermore, narrow bandgap semiconductors, such as germanium (Ge) and InxGa1-xAs, enhance the ON-state current and improve the switching behavior of TFET devices, thus making these materials attractive candidates for further study. Moreover, epitaxial growth of Ge on InxGa1-xAs results in tensile stress (ε) within the Ge thin-film, thereby giving device engineers the ability to tune its material properties (e.g., mobility, bandgap) via strain engineering and in so doing enhance device performance. For these reasons, this research systematically investigates the material, optical, electronic transport, and heterointerfacial properties of ε-Ge/InxGa1-xAs heterostructures grown on GaAs and Si substrates. Additionally, the influence of strain on MOS interfaces with Ge is examined, with specific application toward low-defect density ε-Ge MOS device design. Finally, vertical ε-Ge/InxGa1-xAs tunneling junctions are fabricated and characterized for the first time, demonstrating their viability for the continued development of next-generation low-power nanoelectronic devices utilizing the Ge/InxGa1-xAs material system.

Degree

thesis:*
Name thesis:degree_name
Doctor of Philosophy
Level thesis:degree_level
doctoral
Discipline thesis:degree_discipline
Electrical Engineering
Department dc:contributor.department
Electrical Engineering
Grantor dc:publisher
Virginia Tech
Year dc:date.issued
2024

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Clavel, Michael Brian
Chair dc:contributor.committeechair
  • Hudait, Mantu K.
Committee members dc:contributor.committeemember
  • Heremans, Jean Joseph
  • Orlowski, Mariusz Kriysztof
  • Jia, Xiaoting
  • Lester, Luke F.

Subjects

dc:subject × 8

Rights

dc:rights
Statement dc:rights
  • In Copyright
Language dc:language.iso
en

Identifiers

dc:identifier.*
Dc Identifier Other
vt_gsexam:39362
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/117965

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Clavel, Michael Brian. Tensile-Strained Ge/III-V Heterostructures for Low-Power Nanoelectronic Devices. doctoral thesis, Virginia Tech, 2024. https://hdl.handle.net/10919/117965