Design of energy efficient high speed I/O interfaces

The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2016

Author dc:creator

• Talegaonkar, Mrunmay Vyankatesh

Contributors dc:contributor

• Hanumolu, Pavan Kumar
• Kumar, Rakesh
• Rosenbaum, Elyse
• Shanbhag, Naresh

• digital multiplying delay-locked loop (MDLL)
• digitally-controlled ring oscillator (DCO)
• bit error rate
• rapid on-off bias
• fast turn-on clock multiplier
• energy-proportional operation
• current mode logic output driver
• clock and data recovery (CDR), Mueller-Muller CDR
• baud-rate
• burst-mode
• channel pulse response
• channel estimation
• phase-locked loop (PLL)
• fractional-N PLL
• frequency-to-digital converter
• phase interpolator

Statement dc:rights

• Copyright 2016 Mrunmay Vyankatesh Talegaonkar

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/90871

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/90871