{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/90871"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/90871","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Design of energy efficient high speed I/O interfaces","abstract":"The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.","abstract_html":"The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.","abstract_has_math":false,"creators":["Talegaonkar, Mrunmay Vyankatesh"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan Kumar","Kumar, Rakesh","Rosenbaum, Elyse","Shanbhag, Naresh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-07-07T21:14:23Z","date_published":"2016-07-07T21:14:23Z","updated_at":"2026-07-22T22:26:34Z","subjects":["digital multiplying delay-locked loop (MDLL)","digitally-controlled ring oscillator (DCO)","bit error rate","rapid on-off bias","fast turn-on clock multiplier","energy-proportional operation","current mode logic output driver","clock and data recovery (CDR), Mueller-Muller CDR","baud-rate","burst-mode","channel pulse response","channel estimation","phase-locked loop (PLL)","fractional-N PLL","frequency-to-digital converter","phase interpolator"],"languages":["en"],"rights":["Copyright 2016 Mrunmay Vyankatesh Talegaonkar"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/90871","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan Kumar","Kumar, Rakesh","Rosenbaum, Elyse","Shanbhag, Naresh"]},{"key":"dc:creator","label":"Author","values":["Talegaonkar, Mrunmay Vyankatesh"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2016-07-07T21:14:23Z","2018-07-08T09:15:16Z","2016-03-15","2016-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["digital multiplying delay-locked loop (MDLL)","digitally-controlled ring oscillator (DCO)","bit error rate","rapid on-off bias","fast turn-on clock multiplier","energy-proportional operation","current mode logic output driver","clock and data recovery (CDR), Mueller-Muller CDR","baud-rate","burst-mode","channel pulse response","channel estimation","phase-locked loop (PLL)","fractional-N PLL","frequency-to-digital converter","phase interpolator"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2016 Mrunmay Vyankatesh Talegaonkar"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/90871"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.","Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01","The student, Mrunmay Vyankatesh Talegaonkar, submitted this Dissertation for approval on 2016-03-11 at 14:46.","This Dissertation was approved for publication on 2016-03-15 at 08:51.","DSpace SAF Submission Ingestion Package generated from Vireo submission #9102 on 2016-07-07 at 14:16:14","Made available in DSpace on 2016-07-07T21:14:23Z (GMT). No. of bitstreams: 3 TALEGAONKAR-DISSERTATION-2016.pdf: 8364009 bytes, checksum: 6e6c0881b97d27efba82d3d57944a59b (MD5) LICENSE.txt: 4227 bytes, checksum: 16fa7e36a1560619e87972302c99bbd0 (MD5) PROQUEST_LICENSE.txt: 4573 bytes, checksum: 06dca634fff396b5397a0184d0ca556c (MD5) Previous issue date: 2016-03-15","Embargo set by: Seth Robbins for item 93225 Lift date: 2018-07-07T21:14:52Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 93225 Lift date: 2018-07-07T21:18:16Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 93225 on 2018-07-08T09:15:16Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design of energy efficient high speed I/O interfaces"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan Kumar","Kumar, Rakesh","Rosenbaum, Elyse","Shanbhag, Naresh"],"dc:creator":["Talegaonkar, Mrunmay Vyankatesh"],"dc:date":["2016-07-07T21:14:23Z","2018-07-08T09:15:16Z","2016-03-15","2016-05"],"dc:description":["The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.","Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01","The student, Mrunmay Vyankatesh Talegaonkar, submitted this Dissertation for approval on 2016-03-11 at 14:46.","This Dissertation was approved for publication on 2016-03-15 at 08:51.","DSpace SAF Submission Ingestion Package generated from Vireo submission #9102 on 2016-07-07 at 14:16:14","Made available in DSpace on 2016-07-07T21:14:23Z (GMT). No. of bitstreams: 3 TALEGAONKAR-DISSERTATION-2016.pdf: 8364009 bytes, checksum: 6e6c0881b97d27efba82d3d57944a59b (MD5) LICENSE.txt: 4227 bytes, checksum: 16fa7e36a1560619e87972302c99bbd0 (MD5) PROQUEST_LICENSE.txt: 4573 bytes, checksum: 06dca634fff396b5397a0184d0ca556c (MD5) Previous issue date: 2016-03-15","Embargo set by: Seth Robbins for item 93225 Lift date: 2018-07-07T21:14:52Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 93225 Lift date: 2018-07-07T21:18:16Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 93225 on 2018-07-08T09:15:16Z."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/90871"],"dc:language":["en"],"dc:rights":["Copyright 2016 Mrunmay Vyankatesh Talegaonkar"],"dc:subject":["digital multiplying delay-locked loop (MDLL)","digitally-controlled ring oscillator (DCO)","bit error rate","rapid on-off bias","fast turn-on clock multiplier","energy-proportional operation","current mode logic output driver","clock and data recovery (CDR), Mueller-Muller CDR","baud-rate","burst-mode","channel pulse response","channel estimation","phase-locked loop (PLL)","fractional-N PLL","frequency-to-digital converter","phase interpolator"],"dc:title":["Design of energy efficient high speed I/O interfaces"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:34Z"}