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Showing 1 to 4 of 4 for “"Multiplying delay-locked loop"”.
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Clock multiplication techniques for high-speed I/Os
… reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication …
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Toward realizing power scalable and energy proportional high-speed wireline links
… LC-PLL based clock multi- plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita- tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves power-on-lock in 1ns. The fifth and biggest contribution of this dissertation is the design …
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.
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Dynamic power management for computing and communication
Power management is essential in state-of-the-art many-core processor and system-on-chip designs due to the ever-increasing demand for performance and the diminishing benefits from technology scaling. With more and more integration of processing cores and functional blocks, aggressive power …