High-Level Power Estimation

High-level power estimation requires high-level predictions of circuit average activity, area, and delay, in order to estimate power. The main contribution of this research is development of predictors (estimators) for activity, area, and delay for combinational circuits, thus making it possible to estimate power at the RT level. All of the above predictors work with a functional description of the design and avoid the time consuming translation of the RT description into a circuit-level description, thus making them fast, which in turn enables the designer to explore the area, delay, and power space early in the design.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Nemani, Mahadevamurty

Contributors dc:contributor

• Farid N. Najm

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9904547

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81250