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Showing 1 to 20 of 35 for “"Power Estimation"”.

  1. High-Level Power Estimation

    High-level power estimation requires high-level predictions of circuit average activity, area, and delay, in order to estimate power. The main contribution of this research is development of predictors (estimators) for activity, area, and delay for combinational circuits, thus making it possible to …

    uiuc Repository record for High-Level Power Estimation (opens in a new tab)

  2. Early Power Estimation for VLSI Circuits

    Power estimation for register files at the microarchitectural level requires predictions of activity and capacitance of power hungry nodes in the register file. Both of these predictors are developed in this research, thus making it possible to estimate power for multiported, pipelined register …

    uiuc Repository record for Early Power Estimation for VLSI Circuits (opens in a new tab)

  3. Leakage Models for High Level Power Estimation

    In heutigen sub-100nm CMOS Systemen sind Leckströme von hoher Bedeutung. Diese können auf Transistorebene langsam aber genau (BSIM oder PSP) und auf der Gatter-Ebene schneller aber unter Vernachlässigung wichtiger Parameter (Liberty) vorhergesagt werden. In dieser Arbeit werden Modelle auf RT Ebene …

    oldenburg Repository record for Leakage Models for High Level Power Estimation (opens in a new tab)

  4. Incremental switching factor calculation for power estimation

    Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.

    mit Repository record for Incremental switching factor calculation for power estimation (opens in a new tab)

  5. Market power estimation in the peruvian brewing industry

    … offers an attractive scope for evaluating market power. Following the structure-conduct-performance approach, a nonlinear simultaneous equation model is estimated to measure the degree of market power and to analyse its shifts as the industry undergoes structural changes on a monthly basis …

    utdt Repository record for Market power estimation in the peruvian brewing industry (opens in a new tab)

  6. Power Estimation for High-Performance Lithium-Ion Batteries

    … thesis addresses the challenges associated with power estimation for lithium-ion batteries from both experimental and modeling perspectives. From a safety perspective, accurately determining whether the battery pack can provide the necessary power for a given task is crucial for applications with …

    oxford-brookes Repository record for Power Estimation for High-Performance Lithium-Ion Batteries (opens in a new tab)

  7. Probabilistic simulation for reliability and average power estimation

    … problems such as electromigration in the power buses, hot-carrier degradation of transistors, and excessive power consumption, which ultimately resulted in chip failures. This brought forward the need for simulation tools that would evaluate the susceptibility to the aforementioned hazards …

    uiuc Repository record for Probabilistic simulation for reliability and average power estimation (opens in a new tab)

  8. Power Estimation and Minimization of Digital Signal Processing Systems

    We have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for …

    uiuc Repository record for Power Estimation and Minimization of Digital Signal Processing Systems (opens in a new tab)

  9. Monte Carlo Methods for Reliability Analysis and Power Estimation

    Estimating the power dissipated during normal operating conditions is a major concern in the design of integrated circuits. Since excessive power dissipation causes overheating and can lead to soft errors and permanent damage, attempts to achieve first-pass reliability require accurate and …

    uiuc Repository record for Monte Carlo Methods for Reliability Analysis and Power Estimation (opens in a new tab)

  10. Power estimation and power optimization policies for processor-based systems

    … effective approaches to reduce and estímate the power consumption in processor-based architectures. This work targets embedded systems, inorder and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad to reduce or estimate the power consumption while keeping the …

    upm Repository record for Power estimation and power optimization policies for processor-based systems (opens in a new tab)

  11. High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design

    … (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological …

    vt Repository record for High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design (opens in a new tab)

  12. Investigation of Indoor Propagation Algorithms for Localization Purposes: Simulation and Measurements of Indoor Propagation Algorithms for Localization Applications using Wall Correction Factors, Local Mean Power Estimation and Ray Tracing Validations

    … include indoor propagation behaviour, local mean power estimation, proposing new indoor path loss model and introducing a case study on 60 GHz propagation in indoor environments using ray tracing and measurements. A summary of propagation mechanisms and manifestations in the indoor environment is …

    bradford Repository record for Investigation of Indoor Propagation Algorithms for Localization Purposes: Simulation and Measurements of Indoor Propagation Algorithms for Localization Applications using Wall Correction Factors, Local Mean Power Estimation and Ray Tracing Validations (opens in a new tab)

  13. Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers

    … Submicron (DSM) feature sizes, high-performance power-efficient computer architectures that keep pace with improving technologies need to be explored. Technology scaling increases the effects of wire latencies, inductive effects, noise and crosstalk in on-chip communication, limiting the …

    vt Repository record for Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers (opens in a new tab)

  14. Average-case analysis of power consumption in embedded systems

    Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact …

    cork Repository record for Average-case analysis of power consumption in embedded systems (opens in a new tab)

  15. Bottom-Up High -Level Power Modeling and Estimation

    High-level power estimation requires power macromodel for different blocks which are easy to use and automatically constructed. The main contribution of this research is the development of macromodels for average power, energy for every input vector pair (energy per cycle) and peak-current for …

    uiuc Repository record for Bottom-Up High -Level Power Modeling and Estimation (opens in a new tab)

  16. Design and Implementation of Intelligent Guidance Algorithms for UAV Mission Protection

    … algorithms, a health monitoring system and a power estimation approach. Post-fault conditions are considered as unknown uncertainties that unmanned vehicles could encounter during regular operation missions. In this thesis, three main threats are studied: the presence of unknown obstacles in …

    embry-riddle Repository record for Design and Implementation of Intelligent Guidance Algorithms for UAV Mission Protection (opens in a new tab)

  17. Reducing Power in FPGA Designs Through Glitch Reduction

    … functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. …

    byu Repository record for Reducing Power in FPGA Designs Through Glitch Reduction (opens in a new tab)

  18. Performance Evaluation of Wind Turbine Blades using Blade Element Momentum Theory and Flow Simulation Techniques

    … were compared to those predicted by BEM. The power estimation obtained from CFD was over predicted by 2.7% as compared to BEM. Spanwise vortex structures were observed which were deemed to be the primary cause for a shift in inflow angles along the span of the blade. Also, several 3-D flow …

    ku Repository record for Performance Evaluation of Wind Turbine Blades using Blade Element Momentum Theory and Flow Simulation Techniques (opens in a new tab)

  19. Proton Computed Tomography: a novel calibration approach for proton treatment planning

    … of phantom-based calibration for stopping power estimation, and an initial exploration of clinical applications for proton therapy planning. Collaborative studies with international research groups further demonstrated the potential of integrating pCT and multi-energy CT data to reduce …

    trento Repository record for Proton Computed Tomography: a novel calibration approach for proton treatment planning (opens in a new tab)

  20. Low power, reduced complexity filtering and improved tracking accuracy for GNSS

    This thesis addresses the power consumption problems resulting from the advent of multiple GNSS satellite systems which create the need for receivers supporting multi-frequency, multi-constellation GNSS systems. Such a multi-mode receiver requires a substantial amount of signal processing power

    westminster Repository record for Low power, reduced complexity filtering and improved tracking accuracy for GNSS (opens in a new tab)

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