New Techniques to Verify Timing Correctness of Integrated Circuits

A preliminary study of the relationship between false paths and delay fault testing is also presented. We first show an example where a circuit that does not have any delay variations behaves incorrectly during normal operation due to the common assumptions on false paths used in determining the clock cycle time. We then show an example of a faulty circuit that passes testing because certain false paths contribute to the invalidation of delay tests generated under a single-fault assumption. Finally, we show an example where a good circuit that functions correctly under normal operation is declared as faulty when certain false paths are activated during scan-based testing. For each case, we suggest possible remedies that can sometimes result in more conservative estimates on clock cycle times.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Heragu, Keerthinarayan Prasanna

Contributors dc:contributor

• Patel, Janak H.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI9834687

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81224