Logic upset induced by substrate current during power-on ESD

In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Xiu, Yang

Contributors dc:contributor

• Rosenbaum, Elyse

• power-on electrostatic discharge (ESD)
• soft failure
• substrate current
• system-level electrostatic discharge (ESD)

Statement dc:rights

• Copyright 2014 Yang Xiu

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/73003

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/73003