{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/73003"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/73003","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Logic upset induced by substrate current during power-on ESD","abstract":"In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.","abstract_html":"In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.","abstract_has_math":false,"creators":["Xiu, Yang"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-01-21T19:55:57Z","date_published":"2015-01-21T19:55:57Z","updated_at":"2026-07-22T22:26:07Z","subjects":["power-on electrostatic discharge (ESD)","soft failure","substrate current","system-level electrostatic discharge (ESD)"],"languages":["en"],"rights":["Copyright 2014 Yang Xiu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/73003","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Xiu, Yang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-01-21T19:55:57Z","2017-01-22T10:15:29Z","2014-12","2015-01-21"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["power-on electrostatic discharge (ESD)","soft failure","substrate current","system-level electrostatic discharge (ESD)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2014 Yang Xiu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/73003"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2014-12-01T20:57:31Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Xiu_Yang.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5)","Made available in DSpace on 2015-01-21T19:55:57Z (GMT). No. of bitstreams: 1 Yang_Xiu.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5)","Embargo set by: Seth Robbins for item 73192 Lift date: 2017-01-21T19:56:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 73192 on 2017-01-22T10:15:29Z."]},{"key":"dc:title","label":"Title","values":["Logic upset induced by substrate current during power-on ESD"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Xiu, Yang"],"dc:date":["2015-01-21T19:55:57Z","2017-01-22T10:15:29Z","2014-12","2015-01-21"],"dc:description":["In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size. The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2014-12-01T20:57:31Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Xiu_Yang.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5)","Made available in DSpace on 2015-01-21T19:55:57Z (GMT). No. of bitstreams: 1 Yang_Xiu.pdf: 1248572 bytes, checksum: 2e329e82ee2456a54c6caa2693b35a5d (MD5)","Embargo set by: Seth Robbins for item 73192 Lift date: 2017-01-21T19:56:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 73192 on 2017-01-22T10:15:29Z."],"dc:identifier":["http://hdl.handle.net/2142/73003"],"dc:language":["en"],"dc:rights":["Copyright 2014 Yang Xiu"],"dc:subject":["power-on electrostatic discharge (ESD)","soft failure","substrate current","system-level electrostatic discharge (ESD)"],"dc:title":["Logic upset induced by substrate current during power-on ESD"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:07Z"}