Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 10 of 10 for “"System-Level ESD"”.
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Investigation of system-level ESD-induced failures
Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets …
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Investigating soft failures induced by system-level ESD
Hardware and application-level manifestations of ESD soft failures were characterized for three single-board computers. ESD events were generated following the system-level ESD standard (IEC 61000-4-2), matching real-world testing and events. Soft failures resulting from ESD were seen on all …
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Investigation of system-level ESD induced soft failures
Electrostatic discharge (ESD) is a common phenomenon that can have negative implications for the performance of systems during operation. ESD is a brief, high-current stress that when applied to a functional system, can cause a variety of problems ranging from temporary system malfunction to …
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System level ESD failure mechanisms, analysis and test method
… four papers, discusses three topics related to system level electrostatic discharge. In the first paper, the discharge current and the transient fields of an ESD generator in the contact mode are numerically simulated using the FDTD method...The second and the third papers derived a reference …
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Failures caused by supply fluctuations during system-level ESD
It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be …
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Understanding, modeling, and mitigating system-level ESD in integrated circuits
… several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important …
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Logic upset induced by substrate current during power-on ESD
… during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often involves contention …
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Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach
Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. …
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Characterization and modeling of ESD events and near-field scanning calibration structures
… that cover, two major topics. The first topic, system-level electrostatic discharge (ESD), is discussed over the course of two papers. The second topic, a calibration structure for near-field scanning probe calibration application, is discussed in the last paper. In the first paper, …
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Design, Characterization and Analysis of Component Level Electrostatic Discharge (ESD) Protection Solutions
Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted …