Performance Evaluation of Multiple Register Set Architectures and Cache Memories

Multiple register set architectures have been proposed as a method to reduce the large amount of memory traffic associated with high-level language procedure calls. In this thesis, the effect on overall processor memory traffic of multiple register sets is characterized for a set of real programs. To accomplish this, traces of programs' address and register references were collected on a VAX-11/780. These traces were then mapped to the traces that could have come from a hypothetical VAX with multiple register sets. The memory traffic for various numbers of register sets and numbers of registers per set were compared to the memory traffic in the original trace. The results show a 10-20% reduction in memory traffic using the multiple register sets; the results vary among programs. The effect of context switch was also measured and found not to be significant.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Eickemeyer, Richard James

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Identifier

(UMI)AAI8815338

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69383