Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Multiple register set architectures have been proposed as a method to reduce the large amount of memory traffic associated with high-level language procedure calls. In this thesis, the effect on overall processor memory traffic of multiple register sets is characterized for a set of real programs. To accomplish this, traces of programs' address and register references were collected on a VAX-11/780. These traces were then mapped to the traces that could have come from a hypothetical VAX with multiple register sets. The memory traffic for various numbers of register sets and numbers of registers per set were compared to the memory traffic in the original trace. The results show a 10-20% reduction in memory traffic using the multiple register sets; the results vary among programs. The effect of context switch was also measured and found not to be significant.
Engineering, Electronics and Electrical, Computer Science
University of Illinois - Urbana-Champaign
Networked Digital Library of Theses and Dissertations
University of Illinois at Urbana-Champaign