Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 963 for “"register"”.
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Resonant Binary Shifting Register
Made available in DSpace on 2014-12-04T21:03:15Z (GMT). No. of bitstreams: 1 6001700.pdf: 6502754 bytes, checksum: aed17bf6ac2de7b443bd7982388451da (MD5) Previous issue date: 1960
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Architecture independent register allocation
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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The Capacitor-Coupled Shift Register
Made available in DSpace on 2014-12-10T20:13:33Z (GMT). No. of bitstreams: 1 7309904.pdf: 2442007 bytes, checksum: ad1a51dd02ee8f10582797170463c234 (MD5) Previous issue date: 1972
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Energy-efficient register file design
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2000.
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Transparent spilling and refilling of partitioned overlapping register window register organizations with a remote instruction pointer
Register allocation is critical to processor performance. Registers are the fastest storage system available to a processor. The more capable a register set's organization is at maintaining process context, the fewer the number of memory accesses the processor will need to make. Overlapping …
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Compiler Optimization Effects on Register Collisions
… toward this goal is to keep values in fast registers to limit the number of slower memory accesses that occur. When there are not enough physical registers available for use, values are ``spilled'' to the runtime stack. The need for spills is discovered during register allocation wherein …
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"The Geography of the ""social Register"""
The Social Register is a reliable indicator of upper class status in the United States. This paper explores the intersection of class, status and residency in America. The upper class has used strategic legal constructions such as restrictive land covenants, zoning, municipal incorporation and …
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Nonblocking packet switching with shift-register rings
… design is based on a fast word-parallel shift-register ring, and it is a platform for studying the fundamentals of packet switching.
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Register allocation and optimization techniques in compiler construction
… thesis was to investigate the implementation of register allocation and optimization techniques used in the process of compiler construction. The implementation issues were investigated by choosing an architecture and examining various register allocation and optimization techniques. In choosing …
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Finite-State Morphological Parsing Using Register Vector Grammars
Although the RVGMP can parse some data which Kimmo cannot parse, the RVGMP is slower on average than Kimmo. Poor program design is responsible for this slow time. A revised program design, based in part on a new design for RVG, is proposed. Since the redesigned RVGs have doubled their parsing …
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Compilation of Register Transfer Language Descriptions Into Silicon
… defined cells, and efficient handling of Register Transfer (RT) operators which are represented by Boolean recurrences.
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Aeolous Innovations: The Sonivent Automated HVAC Heating/Cooling Register
Aeolus Innovations is set to roll out a simple and effective product to help save customers money each month on their heating and cooling bill. Our product, the Sonivent, is an easy to install, easy to use vent that is able to fit in any home air duct. By closing off the vent to an unoccupied room, …
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ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC
Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power …
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Multicomputer Interconnection Using Word Parallel Shift Register Ring Networks
This thesis surveys existing processor-memory interconnection structures and investigates the word-parallel ring network in detail. It proposes a design for constructing a multimicrocomputer using such a network. The ring network operates as both a memory switch interconnecting processor nodes and …
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High Quality Test Generation at the Register Transfer Level
… design levels. In particular, exploiting the Register Transfer Level for test generation allows for the use of relational information unavailable at the structural level. This dissertation demonstrates several novel methods for generating tests applicable for both structural and functional …
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Cluster assignment and instruction scheduling for partitioned register-set machines
… constraint enters the picture---the number of register-file ports needed grows directly with the number of functional units. At some point, the multiplexing logic on register ports can come to dominate the processor's cycle time. A reasonable solution is to partition the register file into …
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Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Multiple register set architectures have been proposed as a method to reduce the large amount of memory traffic associated with high-level language procedure calls. In this thesis, the effect on overall processor memory traffic of multiple register sets is characterized for a set of real programs. …
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Initialisation, control and readout of a nuclear-magnon quantum register
… towards a fully fledged magnon-based quantum register.
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